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參數(shù)資料
| 型號： | GL843 |
| 廠商： | Genesys Logic, Inc. |
| 英文描述： | High Speed USB 2.0 With ADF 2-in-1 Scanner Controller |
| 中文描述： | 高速USB 2.0同盟2合1掃描儀控制器 |
| 文件頁數(shù)： | 24/84頁 |
| 文件大小： | 837K |
| 代理商： | GL843 |
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GL843 High Speed USB2.0 With ADF 2-in-1 Scanner Controller For 3x
2000-2006 Genesys Logic Inc. - All rights reserved.
Page 24
Line art scanning : 1 bit image with gamma correction
111
16 clocks/pixel.
Color scanning : 24 bits image with gamma correction
48 bits image without gamma correction
Gray scanning : 8 bits image with gamma correction
16 bits image without gamma correction
Line art scanning : 1 bit image with gamma correction
The hardware will reset this bit during power-on initial process. It can be set and
checked by S/W to know if the power had been turned off or not.
Default is reset.
0 Digital shading gain=8 times system.
1 Digital shading gain=4 times system.
Note: If you want to get more precise image quality,you can set GAIN4 bit.
Select ASIC operation type.
000 Set normal mode to capture AFE image.
001 Set SDRAM bank testing and power-on moving testing for ASIC simulation
010 Pixel count pattern for ASIC image test.
011 Line count pattern for ASIC image test.
100 Counter and adder test for ASIC simulation test.
101 Reserved.
110 Reserved.
111 Reserved.
4 PWRBIT
3 GAIN4
2-0 OPTEST[2:0]
Offset 07h
……………………………………………
..
…………
..
……
..
………
. Default value = 8
’
h00
LAMPSIM
CCDCTL
DRAMCTL
MOVCTL
RAMSEL
FASTDMA
DMASEL
DMARDWR
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7 LAMPSIM
for timer simulation
6 CCDCTL
5 DRAMCTL
4 MOVCTL
3 SRAMSEL
1 DMA access for SRA
2 FASTDMA
DMA access.
for CCD timing control
for SRAM & DRAM access control
for motor driver IC style control
0 DMA access for DRAM.
0 4clocks/access,that is to say 4clocks/16bits or 4clocks/8bits for
1 2clocks/access,that is to say 2clocks/16bits or 2clocks/8bits for
DMA access.
0 MPU access DRAM under command mode.
1 DMA access DRAM under command mode.
0 DMARDWR
0 DMA read DRAM under command mode.
Note: Please do not write other values than 00H into this register under normal condition.
1 DMASEL
Offset 08h
……………………………………………
..
…………
..
……
..
………
. Default value = 8
’
h00
X
X
DECFLAG GMMFFR GMMFFG GMMFFB
R/W
R/W
GMMZR
R/W
GMMZG
R/W
GMMZB
R/W
R/W
R/W
7 RESERVED
6 DECFLAG
5 GMMFFR
-
0 Select gamma table in increment type
1 Select gamma table in decrement type.
0 This function is not enabled
1 Gamma table address FFH of red channel is a special value.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GL850A | USB 2.0 Low-Power HUB Controller |
| GL850A-MNGXX | USB 2.0 Low-Power HUB Controller |
| GL850A-MNNXX | USB 2.0 Low-Power HUB Controller |
| GL850A-MSGXX | USB 2.0 Low-Power HUB Controller |
| GL850A-MSNXX | USB 2.0 Low-Power HUB Controller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GL848 | 制造商:GENESYS 制造商全稱:GENESYS 功能描述:High Speed USB 2.0 |
| GL850 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:USB 2.0 4-PORT HUB Controller |
| GL850A | 制造商:GENESYS 制造商全稱:GENESYS 功能描述:USB 2.0 Low-Power HUB Controller |
| GL850A-MNGXX | 制造商:GENESYS 制造商全稱:GENESYS 功能描述:USB 2.0 Low-Power HUB Controller |
| GL850A-MNNXX | 制造商:GENESYS 制造商全稱:GENESYS 功能描述:USB 2.0 Low-Power HUB Controller |
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