參數(shù)資料
型號: GL843
廠商: Genesys Logic, Inc.
英文描述: High Speed USB 2.0 With ADF 2-in-1 Scanner Controller
中文描述: 高速USB 2.0同盟2合1掃描儀控制器
文件頁數(shù): 14/84頁
文件大?。?/td> 837K
代理商: GL843
GL843 High Speed USB2.0 With ADF 2-in-1 Scanner Controller For 3x
2000-2006 Genesys Logic Inc. - All rights reserved.
Page 14
3.3 Pin Descriptions
Table 3.3 - Pin Descriptions
Pin Name
Type
Description
GPIO1~8,10~20
I/O
General Purpose Input/Output, EEPROM serial data clock or
LCM data bit0
Bi-polar (3967): MT_PH5=RESETJ
MT_PH4=ENABLEJ
MT_PH3=DIR
MT_PH2=STEP
MT_PH1=MS2
MT_PH0=MS1
Bi-polar (3955): MT_PH7=PHASE_A
MT_PH6=PHASE_B
MT_PH5=D2A
MT_PH4=D1A
MT_PH3=D0A
MT_PH2=D2B
MT_PH1=D1B
MT_PH0=D0B
Bi-polar (1939): MT_PH3=IN1
MT_PH2=IN2
MT_PH1=ENA1
MT_PH0=ENA2
Bi-polar (2916 or 6219): MT_PH5=PHASE1
MT_PH4=PHASE2
MT_PH3=I11
MT_PH2=I01
MT_PH1=I12
MT_PH0=I02
Uni-polar(2003): MT_PH3=PHASE A
MT_PH2=PHASE B
MT_PH1=PHASE /A
MT_PH0=PHASE /B
Motor phase 6~7
MT_PH0~5
O
MT_PH6~7
O
ADF_SENR
I/O
ADF sensor for ADF
HOME
I
Document sensor for ADF
Pin Name
Type
Description
CCD_CK1X
O
CCD Shift register clock1 or CIS clock output
CCD_CPX
O
CCD Clamp gate clock or CIS clock output
CCD_TGX
O
CCD Transfer gate clock for R channel or CIS Line start pulse
CCD_CK2X
O
CCD Shift register clock2 or CIS clock output
CCD_RSX
O
CCD Reset gate clock or CIS clock output
CCD_CK3X
O
CCD Shift register clock3
CCD_CK4X
O
CCD Shift register clock4
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