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參數(shù)資料
| 型號： | GL843 |
| 廠商： | Genesys Logic, Inc. |
| 英文描述： | High Speed USB 2.0 With ADF 2-in-1 Scanner Controller |
| 中文描述： | 高速USB 2.0同盟2合1掃描儀控制器 |
| 文件頁數(shù)： | 43/84頁 |
| 文件大?。?/td> | 837K |
| 代理商： | GL843 |
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GL843 High Speed USB2.0 With ADF 2-in-1 Scanner Controller For 3x
2000-2006 Genesys Logic Inc. - All rights reserved.
Page 43
1 Has received data number specified in Reg 88 from RS232.
Offset 50h
……
..
……
..
…………………
..
………
..
…
.
………
..
……
....
…
..
…
.
…
. Default value = 8
’
h00
X
X
X
X
FERDA5
R/W
FERDA4
R/W
FERDA3
R/W
FERDA2
R/W
FERDA1
R/W
FERDA0
R/W
7-6 RESERVED
5-0 FERDA[5:0]
-
Address of control register of front-end in read operation.
Before reading control register of front-end (Reg 46, 47), designers have to
specify address of the control register by writing address to this port.
Offset 51h
……
..
……
..
…………………
..
………
..
…
.
………
..
…
.
…
..
…
..
…
..
…
. Default value = 8
’
h00
X
X
X
X
FEWRA5
R/W
FEWRA4
R/W
FEWRA3
R/W
FEWRA2
R/W
FEWRA1
R/W
FEWRA0
R/W
7-6 RESERVED
5-0 FEWRA[5:0]
-
Address of control register of front-end in write operation.
Before writing control register of front-end (Reg 3A, 3B), designers have to
specify address of the control register by writing address to this port.
Offset 52h
……
..
……
..
…………………
..
………
..
…
.
………
..
…
.
…
..
…
..
…
..
…
. Default value = 8
’
h00
X
X
X
X
X
X
RHI4
R/W
RHI3
R/W
RHI2
R/W
RHI1
R/W
RHI0
R/W
7-5 RESERVED
4-0 RHI[4:0]
-
The latch point for high-byte of R channel of AFE in every pixel.
For example, if a system is designed to have 12 clocks/pixel, and designer wants
to latch the high-byte of R channel at 1
’
st clock in every pixel, designer has to fill
‘
00001
’
to RHI [4:0].
Offset 53h
……
..
……
..
…………………
..
………
..
…
.
………
..
…
.
…
..
…
..
…
..
…
. Default value = 8
’
h00
X
X
X
X
X
X
RLOW4
R/W
RLOW3
R/W
RLOW2
R/W
RLOW1
R/W
RLOW0
R/W
7-5 RESERVED
4-0 RLOW[4:0]
-
The latch point for low-byte of R channel of AFE in every pixel
For example, if a system is designed to have 12 clocks/pixel, and designer wants
to latch the high-byte of R channel at 1
’
st clock in every pixel, designer has to fill
‘
00001
’
to RHI [4:0].
Offset 54h
……
..
……
..
…………………
..
………
..
…
.
………
..
…
.
…
..
…
..
…
..
…
. Default value = 8
’
h00
X
X
X
X
X
X
GHI4
R/W
GHI3
R/W
GHI2
R/W
GHI1
R/W
GHI0
R/W
7-5 RESERVED
4-0 GHI[4:0]
-
The latch point for high-byte of G channel of AFE in every pixel.
相關PDF資料 |
PDF描述 |
|---|---|
| GL850A | USB 2.0 Low-Power HUB Controller |
| GL850A-MNGXX | USB 2.0 Low-Power HUB Controller |
| GL850A-MNNXX | USB 2.0 Low-Power HUB Controller |
| GL850A-MSGXX | USB 2.0 Low-Power HUB Controller |
| GL850A-MSNXX | USB 2.0 Low-Power HUB Controller |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| GL848 | 制造商:GENESYS 制造商全稱:GENESYS 功能描述:High Speed USB 2.0 |
| GL850 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:USB 2.0 4-PORT HUB Controller |
| GL850A | 制造商:GENESYS 制造商全稱:GENESYS 功能描述:USB 2.0 Low-Power HUB Controller |
| GL850A-MNGXX | 制造商:GENESYS 制造商全稱:GENESYS 功能描述:USB 2.0 Low-Power HUB Controller |
| GL850A-MNNXX | 制造商:GENESYS 制造商全稱:GENESYS 功能描述:USB 2.0 Low-Power HUB Controller |
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