參數(shù)資料
型號： GF9330
英文描述： GF9330 - High Performance HDTV/SDTV Deinterlacer
中文描述： GF9330 -高性能高清/標清去隔行掃描
文件頁數(shù)： 9/34頁
文件大?。?/td> 550K
代理商： GF9330
GENNUM CORPORATION
18283 - 3
9
G
AC ELECTRICAL CHARACTERISTICS - SDRAM Interfaces
The SDRAM 1 Interface signals include S1_CLK, S1_CS, S1_RAS, S1_CAS, S1_WE, S1_ADDR[13:0] and S1_DAT[47:0].
The SDRAM 2 Interface signals include S2_CLK, S2_CS, S2_RAS, S2_CAS, S2_WE, S2_ADDR[13:0] and S2_DAT[47:0].
V
DDIO
= 3.0 to 3.6V, V
DDCORE
= 2.25 to 2.75V, T
A
= 0 to 70
°
C, unless otherwise shown
PARAMETER
CONDITIONS
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Clock Input Frequency
F
HSCI_SD
-
85
90
MHz
1
Input Data Setup Time
t
SU_SD
2.0
-
-
ns
1, 2
Input Data Hold Time
t
IH_SD
2.5
-
-
ns
1, 2
Input Clock Duty Cycle
40
-
60
%
1
Output Data Delay Time
V
DDIO
=3.6V,
C
L
=15pF load
t
OD_SD
-
-
9.1
ns
1
Output Data Hold Time
V
DDIO
=3.6V,
C
L
=15pF load
t
OH_SD
2.0
-
-
ns
1
Output Enable Time
V
DDIO
=3.6V,
C
L
=15pF load
t
OEN_SD
-
-
20
ns
1, 4
Output Disable Time
V
DDIO
=3.6V,
C
L
=15pF load
t
ODIS_SD
-
-
20
ns
1, 4
Output Data Rise/Fall Time
V
DDIO
=3.6V,
C
L
=15pF load
t
ODRF_SD
-
-
2.0
ns
1, 3
NOTES:
1. Based on simulation results, verified during device characterization process.
2. 50% levels.
3. 20% to 80% levels.
4. Two clock cycles allocated for data bus turnaround.
AC ELECTRICAL CHARACTERISTICS - Host Interface
The host interface signals include HOST_EN, SER_MD, CS, DAT_IO[7:0], R_W and A_D.
V
DDIO
= 3.0 to 3.6V, V
DDCORE
= 2.25 to 2.75V, T
A
= 0 to 70
°
C, unless otherwise shown.
PARAMETER
CONDITIONS
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Clock Input Frequency
F
HSCI_HI
-
-
20
MHz
1
Input Data Setup Time
t
SU_HI
5
-
-
ns
1, 2
Input Data Hold Time
t
IH_HI
1.5
-
-
ns
1, 2
Input Clock Duty Cycle
40
-
60
%
1
Output Data Delay Time
V
DDIO
=3.6V,
C
L
=15pF load
t
OD_HI
-
-
10.0
ns
1
Output Data Hold Time
V
DDIO
=3.6V,
C
L
=15pF load
t
OH_HI
2.0
-
-
ns
1
Output Enable Time
V
DDIO
=3.6V,
C
L
=15pF load
t
OEN_HI
-
-
15
ns
1
Output Disable Time
V
DDIO
=3.6V,
C
L
=15pF load
t
ODIS_HI
-
-
15
ns
1
Output Data Rise/Fall Time
V
DDIO
=3.6V,
C
L
=15pF load
t
ODRF_HI
-
-
2.0
ns
1, 3
NOTES:
1. Based on simulation results, verified during device characterization process.
2. 50% levels.
3. 20% to 80% levels.
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