參數(shù)資料
型號： GF9330
英文描述： GF9330 - High Performance HDTV/SDTV Deinterlacer
中文描述： GF9330 -高性能高清/標清去隔行掃描
文件頁數(shù)： 25/34頁
文件大?。?/td> 550K
代理商： GF9330
GENNUM CORPORATION
18283 - 3
25
G
6. CLOSED CAPTION BLANKING
The GF9330 provides a blanking function for selected input
video lines. Consecutive lines within each input field are
blanked when this function is enabled, beginning with the
CC_BLANK_START_LINE
and
CC_BLANK_END_LINE. The blanking is applied prior to
any processing of the video data.
ending
with
the
The blanking function is enabled with the CC_BLANK_EN
bit. BLANK_START_LINE and BLANK_END_LINE are each
allocated 8-bits within the host interface.
7. PROGRAMMABLE NOISE REDUCTION AND DETAIL
ENHANCEMENT
The GF9330 performs an efficient technique for high
frequency noise reduction and detail enhancement. There
are 256 levels of control provided by the NOISE_RED[7:0]
bits within the host interface.
High frequency details that are detected with a two-
dimensional high pass filter are enhanced using a non-
linear function mapping between input and output signal.
There are 512 levels of control provided by the
DETAIL_ENH[9:0] bits within the host interface.
8. RESET
The RESET pin will reset all internal logic to it's default
conditions when set LOW. On power up it is recommended
to reset the device to ensure all internal registers are set to
their default state. When applying a reset, the GF9330 will
load in the STD[4:0] and MODE[2:0] settings from the
external pins. If no further configuration is done, these
settings will be used for the operation of the device.
28
11:10
V_BLANK2_LASTLINE[11:0]
UC
Defines the last line of the second blanking
interval.
Auto
14:12
A
DD_LINES_BOTTOM_F1
UC
Defines the number of lines to add to the
bottom of field 1 (not used).
Auto
29
11:0
V_FIELD2_LASTLINE[11:0]
UC
Defines the last line of the second active
video field.
Auto
14:12
A
DD_LINES_TOP_F2
AC
Defines the number of lines to add to the top
of field 2 (not used).
Auto
30
0
EXT_MEMCLK_SEL
AC
Controls the selection of the SDRAM clock
source. For VCLK_IN frequency less than 36
MHz, the internal clock doubler can be used,
in all other modes an external source is
required (MEMCLK_IN).
Auto
1
VOCLK_X1_SEL
AC
Normally set for HD modes where the output
video clock is equal to the input video clock
frequency and is set to '0' for SD cases where
the output video clock is double the video
input clock frequency.
Auto
2
CLK_X1_SE
AC
Normally set for all HD modes and is '0' for all
other cases.
Auto
31
0
S
TART_OPERATION
UC
Using external F_IN, V_IN and H_IN signals,
this parameter must be set following the
completion of programming the F_IN, V_IN
and H_IN offsets.
0
15
CMD_RESET
UC
Forces the GF9330 to enter a reset state. This
commanded reset remains in effect until this
parameter is cleared with a subsequent
command.
0
CONTROL REGISTER DEFINITIONS
(Continued)
ADDRESS
BIT
LOCATION
REGISTER NAME
CLASS
DESCRIPTION
DEFAULT
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相關代理商/技術參數(shù)
參數(shù)描述
GF9330-CBP 制造商:GENNUM 制造商全稱:GENNUM 功能描述:High Performance HDTV/SDTV Deinterlacer
GF9331 制造商:未知廠家 制造商全稱:未知廠家 功能描述:GF9331 - HDTV/SDTV Motion Co-processor
GF9331-CBP 制造商:GENNUM 制造商全稱:GENNUM 功能描述:DTV/SDTV Motion Co-processor
GF9351A-CBE2 制造商:Sigma Designs 功能描述:IC IMAGE PROCESSOR 10BIT DUAL
GF9410\5B 功能描述:MOSFET N-Channel 30V 2A RoHS:否 制造商:STMicroelectronics 晶體管極性:N-Channel 汲極/源極擊穿電壓:650 V 閘/源擊穿電壓:25 V 漏極連續(xù)電流:130 A 電阻汲極/源極 RDS（導通）:0.014 Ohms 配置:Single 最大工作溫度: 安裝風格:Through Hole 封裝 / 箱體:Max247 封裝:Tube
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