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參數(shù)資料
| 型號： | GF9330 |
| 英文描述： | GF9330 - High Performance HDTV/SDTV Deinterlacer |
| 中文描述： | GF9330 -高性能高清/標(biāo)清去隔行掃描 |
| 文件頁數(shù)： | 3/34頁 |
| 文件大?。?/td> | 550K |
| 代理商： | GF9330 |
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GENNUM CORPORATION
18283 - 3
3
G
PIN DESCRIPTIONS
SYMBOL
PIN GRID
TYPE
DESCRIPTION
RESET
A1
I
Active low, asynchronous RESET. Resets all internal logic to
default conditions. Should be applied on power up.
VCLK_IN
F1
I
Video input clock. When the input is SDTV the input clock will be
27, 36, 54 or 72MHz. When the input format is HDTV, the input
clock will be 74.25 or 74.25/1.001MHz.
MEMCLK_IN
H1
I
Memory clock for SDRAM operation to support HD modes,
90MHz input (supplied by an off-chip crystal oscillator).
XVOCLK_IN
J1
I
External video output clock. This input may be used instead of
the internal VCLK_IN clock doubler to supply the video output
clock VCLK_OUT.
XVOCLK_SL
H4
I
Control signal input. When high, selects XVOCLK_IN; when low,
selects the internal VCLK_IN clock doubler for generation of the
video output VCLK_OUT signal.
Y_IN[9:0]
B1,C1,C2,C3,D1,
D2,D3,E1,E2,E3
I
10/8-bit input bus for separate luminance or multiplexed
luminance and colour difference video data. When supplying
8-bit data to the GF9330, Y_IN[1:0] will be set low and the 8-bit
data supplied to Y_IN[9:2].
C_IN[9:0]
J3,J4,K1,K2,K3,
K4,L4,L3,L2,L1
I
10/8-bit input bus for colour difference for video data. When
supplying 8-bit data to the GF9330, C_IN[1:0] will be set low
and the 8-bit data supplied to C_IN[9:2].
FIL_SEL[3:0]
M4,M3,M2,M1
I
Filter selection control bus. FIL_SEL[3:0] are used to switch the
GF9330
’
s internal directional filters on a pixel by pixel basis.
FIL_SEL[3:0] is supplied by the GF9331.
F_IN
N2
I
Video timing control. F_IN identifies the ODD and EVEN fields in
the incoming video signal. F_IN will be low in Field 1 and high
in Field 2.
V_IN
N3
I
Video timing control. V_IN represents the vertical blanking
signal associated with the incoming video signal. V_IN is high
during the vertical blanking interval and low during active video.
H_IN
N4
I
Video timing control. H_IN represents the horizontal blanking
signal associated with the incoming video signal. H_IN is high
during horizontal blanking and low during active video.
FVH_EN
N1
I
Control signal input. When high, the F_IN, V_IN, and H_IN input
pins will be used for video data signalling. When low,
embedded TRS
’
s will be detected for video data timing.
FF_EN
P4
I
Control signal input. When high, FF_EN enables the GF9330
’
s
internal freeze frame compensation. See Section 11.4.
LOCK_22
J2
I
Control signal input. For 2:2 pull-down compensation, the
LOCK_22 pin will be used to identify the presence of a 2:2
sequence in the input video stream.
STD[4:0]
G2,G3,G4,H2,H3
I
Video format definition. Defines the video standard when
operating without the host interface. See Table 1.
MODE[2:0]
F2,F3,F4
I
Operating mode selection. Defines the mode of operation when
operating without the host interface. See Section 9.
HOST_EN
E4
I
Host interface enable. When set high, the GF9330 will be
configured through the host interface. On a high to low transition
of HOST_EN the GF9330 will replace all register settings in the
host interface with the values present on the external pins of the
device including: STD[4:0], MODE[2:0], FVH_EN, FF_EN and
XVOCLK_SL.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GF9331 | GF9331 - HDTV/SDTV Motion Co-processor |
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| GF9926 | TRANSISTOR | MOSFET | MATCHED PAIR | N-CHANNEL | 20V V(BR)DSS | 6A I(D) | SO |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GF9330-CBP | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:High Performance HDTV/SDTV Deinterlacer |
| GF9331 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:GF9331 - HDTV/SDTV Motion Co-processor |
| GF9331-CBP | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:DTV/SDTV Motion Co-processor |
| GF9351A-CBE2 | 制造商:Sigma Designs 功能描述:IC IMAGE PROCESSOR 10BIT DUAL |
| GF9410\5B | 功能描述:MOSFET N-Channel 30V 2A RoHS:否 制造商:STMicroelectronics 晶體管極性:N-Channel 汲極/源極擊穿電壓:650 V 閘/源擊穿電壓:25 V 漏極連續(xù)電流:130 A 電阻汲極/源極 RDS（導(dǎo)通）:0.014 Ohms 配置:Single 最大工作溫度: 安裝風(fēng)格:Through Hole 封裝 / 箱體:Max247 封裝:Tube |
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