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參數(shù)資料
| 型號： | GF9330 |
| 英文描述： | GF9330 - High Performance HDTV/SDTV Deinterlacer |
| 中文描述： | GF9330 -高性能高清/標(biāo)清去隔行掃描 |
| 文件頁數(shù)： | 19/34頁 |
| 文件大?。?/td> | 550K |
| 代理商： | GF9330 |
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GENNUM CORPORATION
18283 - 3
19
G
5.3 Control Register Definition
The host interface internal registers are divided into three
classes: User Configurable (UC), Auto-Configurable (AC),
and Read-Only (RO). Address locations 0 through 14
contain parameters which may be configured by the user.
Locations 15 through 31 are automatically configured
based on the STD[4:0] and MODE[2:0] registers, but can
be user configured if desired.
Address 0 contains three status registers LOCK_32,
FF_DETECT, and SEQUENCE[3:0] which can only be read.
Writing to the read-only registers will have no effect on their
contents.
CONTROL REGISTER DEFINITIONS
ADDRESS
BIT
LOCATION
REGISTER NAME
CLASS
DESCRIPTION
DEFAULT
0
4:0
STD[4:0]
UC
Defines the video standard as described in
Section 1.
00000
7:5
MODE[2:0]
UC
Defines the GF9330 operating mode as
shown below:
000: Interlaced to Progressive Mode
001: Field Merging Mode
010: Film Rate Down Conversion Mode
011: Film Rate Down Conversion (Progressive
Segmented Frame) Mode
111: Bypass Mode (Video Pass Through
Mode)
000
11:8
SEQUENCE[3:0]
RO
Provides the detected field sequence number
from the 3:2 detection circuit.
Calculated
12
FF_DETECT
RO
Set to '1' if a video freeze frame has been
detected.
Calculated
13
LOCK_32
RO
Set to '1' if a 3:2 video sequence has been
detected.
Calculated
1
1:0
FF_MODE[1:0]
UC
Default value = 01, Defines the freeze frame
operating mode as shown below:
00: Manual freeze frame detection/
compensation
01: Automatic freeze frame detection/
compensation
10: Disabled
11: Reserved
01
2
FF_EN_BIT
UC
Enables (1) or disables (0) freeze frame
detection/compensation when in manual
freeze frame mode, i.e. FF_MODE = 00.
01
5:4
MD_MODE[1:0]
UC
Defines the motion detection and
compensation mode as shown below:
00: Disabled
01: Automatic
10: Reserved
11: Reserved
01
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GF9331 | GF9331 - HDTV/SDTV Motion Co-processor |
| GF9410 | TRANSISTOR | MOSFET | N-CHANNEL | 30V V(BR)DSS | 7A I(D) | SO |
| GF9926 | TRANSISTOR | MOSFET | MATCHED PAIR | N-CHANNEL | 20V V(BR)DSS | 6A I(D) | SO |
| GF9926D | TRANSISTOR | MOSFET | N-CHANNEL | 20V V(BR)DSS | 6A I(D) | CHIP |
| GH06505T1A | LASER DIODE |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GF9330-CBP | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:High Performance HDTV/SDTV Deinterlacer |
| GF9331 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:GF9331 - HDTV/SDTV Motion Co-processor |
| GF9331-CBP | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:DTV/SDTV Motion Co-processor |
| GF9351A-CBE2 | 制造商:Sigma Designs 功能描述:IC IMAGE PROCESSOR 10BIT DUAL |
| GF9410\5B | 功能描述:MOSFET N-Channel 30V 2A RoHS:否 制造商:STMicroelectronics 晶體管極性:N-Channel 汲極/源極擊穿電壓:650 V 閘/源擊穿電壓:25 V 漏極連續(xù)電流:130 A 電阻汲極/源極 RDS（導(dǎo)通）:0.014 Ohms 配置:Single 最大工作溫度: 安裝風(fēng)格:Through Hole 封裝 / 箱體:Max247 封裝:Tube |
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