參數(shù)資料
型號(hào)： GF9330
英文描述： GF9330 - High Performance HDTV/SDTV Deinterlacer
中文描述： GF9330 -高性能高清/標(biāo)清去隔行掃描
文件頁(yè)數(shù)： 11/34頁(yè)
文件大?。?/td> 550K
代理商： GF9330
GENNUM CORPORATION
18283 - 3
11
G
2. INPUT SYNCHRONIZATION
The GF9330 obtains relevant timing information from either
embedded TRS information or externally supplied H_IN,
V_IN and F_IN signals.
When FVH_EN is set high, using either the host interface or
the external pin, the GF9330 relies on the externally
supplied H_IN, V_IN and F_IN signals for timing information.
When FVH_EN is set LOW, the GF9330 will extract the
embedded TRS timing information from the video data
stream and will ignore any timing information present on the
F_IN, V_IN and H_IN pins.
2.1 Support for both 8-bit and 10-bit input data
The GF9330 supports 8 and 10-bit input data. When
operating with 8-bit input data, the two LSBs of the
GF9330
’
s 10-bit input should be set LOW and the input data
is applied to the 8 MSBs of the input bus.
2.2 Generic Input Format Signaling
The GF9330 supports generic input data formats with either
4:1:1 or 4:2:2 sampling structures handling up to 2046
active samples per line with a total maximum line width of
4096 (active + blanking) samples. In addition, there is a
limit of 2048 lines per interlaced frame. The following host
interface parameters are used to describe the generic input
data format relative to the F_IN, V_IN and H_IN signals.
See Figure 2.
2.2.1 OUTPUT H_BLANK_SIZE
This parameter defines the number of samples that
comprise the horizontal blanking region. This parameter has
a maximum value of 4095 and is to be less than the total
line width (active + blanking) sample size. Twelve bits within
the host interface are dedicated to this parameter. The
GF9330 only stores and processes active video samples
only (i.e. H_IN=0).
19
10011
720p (50Hz) SMPTE 296M-2001. Y data applied to Y_IN. Cb Cr data applied to C_IN.
Note: Input clock is 74.25MHz.
20
10100
1080p (25Hz) SMPTE 274M. Y data applied to Y_IN. Cb Cr data applied to C_IN.
Note: Input clock is 74.25MHz.
21
10101
720p (25Hz) SMPTE 296M-2001. Y data applied to Y_IN. Cb Cr data applied to C_IN.
Note: Input clock is 74.25MHz.
22
10110
1080p (24 & 24/1.001Hz) SMPTE 274M. Y data applied to Y_IN. Cb Cr data applied to C_IN.
Note: Input clock is 74.25MHz or 74.25/1.001MHz.
23
10111
720p (24 & 24/1.001Hz) SMPTE 296M-2001. Y Data applied to Y_IN. Cb Cr data applied to C_IN.
Note: Input clock is 74.25MHz or 74.25/1.001MHz.
24
11000
1080i (30 & 30/1.001Hz) SMPTE 274M. Y data applied to Y_IN. Cb Cr data applied to C_IN.
Note: Input clock is 74.25MHz or 74.25/1.001MHz.
25
11001
1080p (30 & 30/1.001Hz in Segmented Frame Format) SMPTE RP211-2000. Y data applied to Y_IN.
Cb Cr data applied to C_IN. Note: Input clock is 74.25MHz or 74.25/1.001MHz.
26
11010
1080i (25Hz) SMPTE 274. Y data applied to Y_IN. Cb Cr data applied to C_IN.
Note: Input clock is 74.25MHz.
27
11011
1080p (25 Hz in Segmented Frame Format) SMPTE RP211-2000. Y data applied to Y_IN. Cb Cr data applied
to C_IN. Note: Input clock is 74.25MHz.
28
11100
1080i (25Hz) SMPTE 295M. Y data applied to Y_IN. Cb Cr data applied to C_IN.
Note: Input clock is 74.25MHz.
29
11101
1080p (24 & 24/1.001Hz in Segmented Frame Format) SMPTE RP211-2000. Y data applied to Y_IN.
Cb Cr data applied to C_IN. Note: Input clock is 74.25MHz or 74.25/1.001MHz.
30
11110
1035i (30Hz) SMPTE 260M. Y data applied to Y_IN. Cb Cr data applied to C_IN.
Note: Input clock is 74.25MHz.
31
11111
Generic HD input data format with 4:2:2 sampling and a separate Y/C format. Y data applied to Y_IN.
Cb Cr data applied to C_IN. Externally supplied F_IN, V_IN and H_IN signals are used to synchronize the
input data stream. Note: Input clock is 74.25MHz or 74.25/1.001MHz.
TABLE 1: Encoding of STD[4:0] for Selecting Input Data Format (Continued)
STD
STD[4:0]
DESCRIPTION
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