參數(shù)資料
型號(hào)： GF9330
英文描述： GF9330 - High Performance HDTV/SDTV Deinterlacer
中文描述： GF9330 -高性能高清/標(biāo)清去隔行掃描
文件頁(yè)數(shù)： 32/34頁(yè)
文件大小： 550K
代理商： GF9330
GENNUM CORPORATION
18283 - 3
32
G
11.1 Internal 3:2 Detection
When set to operate in internal 3:2 detect mode, the
GF9330 can automatically detect a 3:2 pull-down sequence
in the incoming video data stream. If a 3:2 sequence is
detected, the GF9330 sets the LOCK_32 control bit in the
host interface to
‘
1
’
. The LOCK_32 pin is also asserted
HIGH once the sequence has been detected.
The actual 3:2 sequence information is reported in the
SEQUENCE[3:0] register within the host interface and on
the XSEQ[3:0] pins. Refer to Figure 11 for a pictorial
representation of the 3:2 sequence reporting.
11.2 External 3:2 Detection
When set to operate in external mode, the user will supply the
3:2 sequence information to the XSEQ[3:0] pins. The GF9330
uses this information to properly de-interlace the input signal
or to perform 60Hz to 24Hz conversion depending on the
state of the MODE[2:0] register in the host interface or
MODE[2:0] pins.
When operating in this mode the input 3:2 sequence
information relates to the input data stream. The 3:2
sequence information requires updating during the first
blank line of the vertical blanking interval, identifying the
sequence number for the following field.
11.3 Sequence Detection and Compensation
The GF9330 supports external 2:2 sequence detection. A
LOCK_22 pin is provided to indicate the presence of a 2:2
sequence.
The
sequence
embedded in the interlaced video input data, and is
identified with the F_IN signal (either derived from the
embedded TRSs or supplied from the external pin). The
LOCK_22 signal will be updated during the first line of each
vertical blanking interval.
information
is
inherently
11.4
Static and Freeze Frame Detection/Compensation
The GF9330 operates in either disabled, automatic or
manual mode for detection and compensation of freeze
frame conditions within the video input stream. When set to
operate
in
disabled
mode
FF_MODE=10), the GF9330 disables the internal freeze
frame detection and compensation circuitry and also
ignores any information presented to the FF_EN pin or the
host interface bit, FF_EN_BIT. When set to operate in
automatic mode (FF_MODE[2:0]=01) the GF9330 internally
detects and compensates for freeze frame situations. When
a freeze frame situation is detected, the GF9330 reports this
in the FF_DETECT status bit found in the host interface. This
bit is updated at the beginning of a field and remains valid
for the remainder of the field. When set to operate in manual
mode (FF_MODE=00) the GF9330 monitors the FF_EN pin
and the host interface bit, FF_EN_BIT to enable or disable
freeze frame compensation. Static and freeze frame
detection compensation is further described in Table 10.
(host
interface
bits,
In order to manually force the freeze frame detector in the
GF9330 into freeze in static or freeze in motion, the
following parameters must be set as follows:
1. Freeze in Static: Uses the temporal filter only.
MSF = 7FFFh
FF_DET_HV = 0000h
FF_EN_BIT = 1
2. Freeze in motion: Uses both the vertical and temporal
filter.
MSF = 0000h
FF_DET_HV = FFFFh
FF_EN_BIT = 0
Note: When using the freeze in motion settings when the
image is static, there will be vertical ringing along the
horizontal edges.
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