參數(shù)資料
型號(hào)： FT2232C
廠商： Electronic Theatre Controls, Inc.
英文描述： FT2232C Dual USB UART / FIFO I.C.
中文描述： FT2232C雙USB的UART / FIFO的集成電路
文件頁數(shù)： 5/51頁
文件大?。?/td> 907K
代理商： FT2232C
DS2232C Version 1.4
Future Technology Devices International Ltd. 2005 Page 5 of 54
FT2232C Dual USB UART / FIFO I.C.
Enhanced Asynchronous Bit-Bang Interface
The FT2232C supports FTDI’s BM chip Bit Bang
mode. In Bit Bang mode, the eight FIFO data lines
can be switched between FIFO interface mode and
an 8-bit Parallel IO port. Data packets can be sent
to the device and they will be sequentially sent to
the interface at a rate controlled by an internal timer
(equivalent to the baud rate prescaler). With the
FT2232C device this mode has been enhanced
so that the internal RD# and WR# strobes are now
brought out of the device which can be used to allow
external logic to be clocked by accesses to the Bit-
Bang IO bus.
Synchronous Bit-Bang Interface
Synchronous Bit-Bang Mode differs from
Asynchronous Bit-Bang mode in that the device
is only read when it is written to. Thus making it
easier for the controlling program to measure the
response to an output stimulus as the data returned
is synchronous to the output data.
High Output Drive Level Capabillity
The IO interface pins can be made to drive out at
three times the standard drive level thus allowing
multiple devices, or devices that require a greater
drive strength to be interfaced to the FT2232C. This
option is configured in the external EEPROM, ad can
be set individually for each channel.
Multi-Protocol Synchronous Serial Engine
Interface (M.P.S.S.E.)
The Multi-Protocol Synchronous Serial Engine
(MPSSE) interface is a new option designed to
interface efficiently with synchronous serial protocols
such as JTAG and SPI Bus. It is very flexible in that it
can be configured for different industry standards, or
proprietary bus protocols. For instance, it is possible
to connect one of the FT2232C’s channels to an
SRAM configurable FPGA as supplied by vendors
such as Altera and Xilinx. The FPGA device would
normally be un-configured (i.e. have no defined
function) at power-up. Application software on the PC
could use the MPSSE to download configuration data
to the FPGA over USB. This data would define the
hardware’s function on power up. The other FT2232
channel would be available for other devices.
This approach would allow a customer to create a
“generic” USB peripheral, who’s hardware function
can be defined under control of the application
software. The FPGA based hardware could be easily
upgraded or totally changed simply by changing the
FPGA configuration data file. (See FTDI’s MORPH-
IC development module for a practicle example,
)
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
FT2232C_04 制造商:FTDI 制造商全稱:FTDI 功能描述:Dual USB UART / FIFO I.C.
FT2232D 制造商:Future Technology Devices International 功能描述:UART 2-CH 3.3V/5V 48-Pin LQFP 制造商:Future Technology Devices International 功能描述:UART 2-CH 3.3V/5V 48-Pin LQFP Bulk 制造商:Future Technology Devices International (FTDI Chip) 功能描述:USB Full Speed to Dual Channel Serial UART/FIFO/JTAG/SPI/I2C IC - LQFP-48
FT2232D/TR 制造商:Future Technology Devices International (FTDI Chip) 功能描述:USB-UART/FIFO SMD 2232 LQFP48 制造商:Future Technology Devices International (FTDI Chip) 功能描述:USB-UART/FIFO, SMD, 2232, LQFP48 制造商:Future Technology Devices International (FTDI Chip) 功能描述:USB-UART/FIFO, SMD, 2232, LQFP48; USB Type:FIFO; USB Version:2.0; Supply Voltage Min:3V; Supply Voltage Max:5.25V; Digital IC Case Style:LQFP; No. of Pins:48; Data Rate:12Mbps; No. of Ports:2; Operating Temperature Min:-40C ;RoHS Compliant: Yes
FT2232D-REEL 功能描述:USB 接口集成電路 USB to Dual UART/ FIFO/SPI/JTAG/I2C RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20
FT2232D-TRAY 制造商:Future Technology Devices International (FTDI Chip) 功能描述:DUAL USB TO SERIAL UART/FIFO IC
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