參數(shù)資料
型號(hào)： FT2232C
廠商： Electronic Theatre Controls, Inc.
英文描述： FT2232C Dual USB UART / FIFO I.C.
中文描述： FT2232C雙USB的UART / FIFO的集成電路
文件頁(yè)數(shù)： 40/51頁(yè)
文件大?。?/td> 907K
代理商： FT2232C
DS2232C Version 1.4
Future Technology Devices International Ltd. 2005 Page 40 of 54
FT2232C Dual USB UART / FIFO I.C.
9.6 Multi-Protocol Synchronous Serial Engine (MPSSE) Mode Signal Descriptions and
Interface Configurations
MPSSE Mode is designed to allow the FT2232C to interface efficiently with synchronous serial protocols such
as JTAG and SPI Bus. It can also be used to program SRAM based FPGA’s over USB. The MPSSE interface is
designed to be flexible so that it can be configured to allow any synchronous serial protocol (industry standard or
proprietary) to be interfaced to the FT2232C. MPSSE is available on channel A only.
MPSSE is fully configurable, and is programmed by sending commands down the data pipe. These can be sent
individually, or more efficiently in packets. MPSSE is capable of a maximum sustained data rate of
5.6 Mega bits / s
.
When Channel A is configured in MPSSE mode the IO signal lines are configured as follows :-
Pin#
(Channel A Only)
24
23
22
21
20
19
17
Signal
Type
Description
TCK/SK
TDI/D0
TDO/DI
TMS/CS
GPIOL0
GPIOL1
GPIOL2
OUTPUT
OUTPUT
INPUT
OUTPUT
I/O
I/O
I/O
Clock signal Output
Serial Data Out
Serial Data In
**Note 27
Select Signal Out
General Pupose input / Output
**Note 27
General Pupose input / Output
**Note 27
General Pupose input / Output
**Note 27
16
15
13
12
11
GPIOL3
GPIOH0
GPIOH1
GPIOH2
GPIOH3
I/O
I/O
I/O
I/O
I/O
General Pupose input / Output
**Note 27
General Pupose input / Output
**Note 27
General Pupose input / Output
**Note 27
General Pupose input / Output
**Note 27
General Pupose input / Output
**Note 27
**Note 27 :
In Input Mode, these pins are pulled to VCCIO via internal 200K resistors. These can be programmed to
gently pull low during USB suspend ( PWREN# = “1” ) by setting this option in the EEPROM.
Enabling
MPSSE mode is enabled using Set Bit Bang Mode driver command. A hex value of 2 will enable it, and a hex value of
0 will reset the device. See application note
AN2232C-02, “Bit Mode Functions for the FT2232C”
for more details
and examples.
The MPSSE command set is fully described in application note
AN2232C-01 - “Command Processor For MPSSE
and MCU Host Bus Emulation Modes”
.
相關(guān)PDF資料
PDF描述
FT245BL FT245BL USB FIFO ( USB - Parallel ) I.C.
FT245BM FT245BM USB FIFO ( USB - Parallel ) I.C.
FT245BQ FT245BQ USB FIFO ( USB - Parallel ) I.C.
FT6116 2K X 8 CMOS SRAM
FT8U100AX FT8U100AX USB Compound Hub Controller
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
FT2232C_04 制造商:FTDI 制造商全稱:FTDI 功能描述:Dual USB UART / FIFO I.C.
FT2232D 制造商:Future Technology Devices International 功能描述:UART 2-CH 3.3V/5V 48-Pin LQFP 制造商:Future Technology Devices International 功能描述:UART 2-CH 3.3V/5V 48-Pin LQFP Bulk 制造商:Future Technology Devices International (FTDI Chip) 功能描述:USB Full Speed to Dual Channel Serial UART/FIFO/JTAG/SPI/I2C IC - LQFP-48
FT2232D/TR 制造商:Future Technology Devices International (FTDI Chip) 功能描述:USB-UART/FIFO SMD 2232 LQFP48 制造商:Future Technology Devices International (FTDI Chip) 功能描述:USB-UART/FIFO, SMD, 2232, LQFP48 制造商:Future Technology Devices International (FTDI Chip) 功能描述:USB-UART/FIFO, SMD, 2232, LQFP48; USB Type:FIFO; USB Version:2.0; Supply Voltage Min:3V; Supply Voltage Max:5.25V; Digital IC Case Style:LQFP; No. of Pins:48; Data Rate:12Mbps; No. of Ports:2; Operating Temperature Min:-40C ;RoHS Compliant: Yes
FT2232D-REEL 功能描述:USB 接口集成電路 USB to Dual UART/ FIFO/SPI/JTAG/I2C RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20
FT2232D-TRAY 制造商:Future Technology Devices International (FTDI Chip) 功能描述:DUAL USB TO SERIAL UART/FIFO IC
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*