參數(shù)資料
型號(hào)： FDC37B80X
廠商： STANDARD MICROSYSTEMS CORP
元件分類： 外設(shè)及接口
英文描述： PC98/99 Compliant Enhanced Super I/O Controller with Keyboard/Mouse Wake-Up
中文描述： MULTIFUNCTION PERIPHERAL, PQFP100
封裝： QFP-100
文件頁(yè)數(shù)： 120/194頁(yè)
文件大小： 802K
代理商： FDC37B80X
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120
Keyboard Data Write
This is an 8 bit write only register. When
written, the C/D status bit of the status register
is cleared to zero and the IBF bit is set.
Keyboard Data Read
This is an 8 bit read only register. If enabled by
"ENABLE FLAGS", when read, the KIRQ output
is cleared and the OBF flag in the status register
is cleared. If not enabled, the KIRQ and/or
AUXOBF1 must be cleared in software.
Keyboard Command Write
This is an 8 bit write only register. When
written, the C/D status bit of the status register
is set to one and the IBF bit is set.
Keyboard Status Read
This is an 8 bit read only register. Refer to the
description of the Status Register for more
information.
CPU-to-Host Communication
The FDC37B80x CPU can write to the Output
Data register via register DBB. A write to
this register automatically sets Bit 0 (OBF) in
the Status register. See Table 49.
Table 49 - Host Interface Flags
8042 INSTRUCTION
OUT DBB
FLAG
Set OBF, and, if enabled, the KIRQ output signal goes high
Host-to-CPU Communication
The host system can send both commands and
data to the Input Data register. The CPU
differentiates between commands and data by
reading the value of Bit 3 of the Status register.
When bit 3 is "1", the CPU interprets the register
contents as a command. When bit 3 is "0", the
CPU interprets the register contents as data.
During a host write operation, bit 3 is set to "1" if
SA2 = 1 or reset to "0" if SA2 = 0.
KIRQ
If "EN FLAGS" has been executed and P24 is
set to a one: the OBF flag is gated onto KIRQ.
The KIRQ signal can be connected to system
interrupt to signify that the FDC37B80x CPU has
written to the output data register via "OUT
DBB,A". If P24 is set to a zero, KIRQ is forced
low. On power-up, after a valid RST pulse has
been delivered to the device, KIRQ is reset to 0.
KIRQ will normally reflects the status of writes
"DBB". (KIRQ is normally selected as IRQ1 for
keyboard support.)
If "EN FLAGS” has not been executed: KIRQ
can be controlled by writing to P24. Writing a
zero to P24 forces KIRQ low; a high forces
KIRQ high.
MIRQ
If "EN FLAGS" has been executed and P25 is
set to a one:; IBF is inverted and gated onto
MIRQ. The MIRQ signal can be connected to
system interrupt to signify that the FDC37B80x
CPU has read the DBB register.
If "EN FLAGS” has not been executed, MIRQ is
controlled by P25, Writing a zero to P25 forces
MIRQ low, a high forces MIRQ high. (MIRQ is
normally selected as IRQ12 for mouse support).
Gate A20
A general purpose P21 is used as a software
controlled Gate A20 or user defined output.
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