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參數(shù)資料
| 型號： | FDC37B80X |
| 廠商： | STANDARD MICROSYSTEMS CORP |
| 元件分類： | 外設(shè)及接口 |
| 英文描述： | PC98/99 Compliant Enhanced Super I/O Controller with Keyboard/Mouse Wake-Up |
| 中文描述： | MULTIFUNCTION PERIPHERAL, PQFP100 |
| 封裝： | QFP-100 |
| 文件頁數(shù)： | 105/194頁 |
| 文件大?。?/td> | 802K |
| 代理商： | FDC37B80X |
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105
Internal PWRGOOD
An internal PWRGOOD logical control is
included to minimize the effects of pin-state
uncertainty in the host interface as V
cc
cycles on
and off. When the internal PWRGOOD signal is
“1” (active), V
cc
is > 3.7V, and the FDC37B80x
host interface is active. When the internal
PWRGOOD signal is “0” (inactive), V
cc
is
≤
3.7V, and the FDC37B80x host interface is
inactive; that is, ISA bus reads and writes will
not be decoded.
The FDC37B80x device pins nPME, KDAT,
MDAT, IRRX, nRI1, nRI2 and RXD2 are part of
the PME interface and remain active when the
internal PWRGOOD signal has gone inactive,
provided V
TR
is powered.
Note: If V
TR
is to be used for programmable
wake-up events when V
CC
is removed, V
TR
must
be at its full minimum potential at least 10
μ
s
before V
cc
begins a power-on cycle. When V
TR
and V
cc
are fully powered, the potential
difference between the two supplies must not
exceed 500mV.
TABLE 43 - FDC37B80x PLL CONTROLS AND SELECTS
PLL CONTROL
(CR24.1)
(CR22.7)
PWRGOOD
1
X
0
0
0
0
0
1
0
1
PME POWER
INTERNAL
DESCRIPTION
X
0
1
0
1
14 MHz PLL Powered Down
Reserved
14MHz PLL Powered, Selected.
Reserved
Reserved
Register Behavior
Table 44 illustrates the AT and PS/2 (including
Model 30) configuration registers available and
the type of access permitted. In order to
maintain software transparency, access to all
the registers must be maintained. As Table 44
shows, two sets of registers are distinguished
based on whether their access results in the part
remaining in powerdown state or exiting it.
Access to all other registers is possible without
awakening the part. These registers can be
accessed during powerdown without changing
the status of the part. A read from these
registers will reflect the true status as shown in
the register description in the FDC description. A
write to the part will result in the part retaining
the data and subsequently reflecting it when the
part awakens. Accessing the part during
powerdown may cause an increase in the power
consumption by the part. The part will revert
back to its low power mode when the access
has been completed.
Pin Behavior
The FDC37B80x is specifically designed for
systems in which power conservation is a
primary concern. This makes the behavior of
the pins during powerdown very important.
The pins of the FDC37B80x can be divided into
two major categories: system interface and
floppy disk drive interface. The floppy disk drive
pins are disabled so that no power will be drawn
through the part as a result of any voltage
applied to the pin within the part's power supply
range. Most of the system interface pins are left
active to monitor system accesses that may
wake up the part.
System Interface Pins
Table 45 gives the state of the system interface
pins in the powerdown state. Pins unaffected by
the powerdown are labeled "Unchanged". Input
pins are "Disabled" to prevent them from
causing currents internal to the FDC37B80x
when they have indeterminate input values.
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