
2–42
Altera Corporation
Stratix II Device Handbook, Volume 1
May 2007
Digital Signal Processing Block
Table 2–5 shows the number of DSP blocks in each Stratix II device.
DSP block multipliers can optionally feed an adder/subtractor or
accumulator in the block depending on the configuration. This makes
routing to ALMs easier, saves ALM routing resources, and increases
performance, because all connections and blocks are in the DSP block.
Additionally, the DSP block input registers can efficiently implement shift
registers for FIR filter applications, and DSP blocks support Q1.15 format
rounding and saturation.
Figure 2–28 shows the top-level diagram of the DSP block configured for
18 × 18-bit multiplier mode.
Table 2–5. DSP Blocks in Stratix II Devices
Device
DSP Blocks
Total 9 × 9
Multipliers
Total 18 × 18
Multipliers
Total 36 × 36
Multipliers
EP2S15
12
96
48
12
EP2S30
16
128
64
16
EP2S60
36
288
144
36
EP2S90
48
384
192
48
EP2S130
63
504
252
63
EP2S180
96
768
384
96
(1)
Each device has either the numbers of 9 × 9-, 18 × 18-, or 36 × 36-bit multipliers
shown. The total number of multipliers for each device is not the sum of all the
multipliers.