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鐩搁棞(gu膩n)PDF璩囨枡	PDF鎻忚堪
AGM36DTBD	CONN EDGECARD 72POS R/A .156 SLD
EP1S30F1020C7	IC STRATIX FPGA 30K LE 1020-FBGA
DS1230YP-70IND+	IC NVSRAM 256KBIT 70NS 34PCM
EP1SGX25DF1020C7	IC STRATIX GX FPGA 25K 1020-FBGA
DS1225AB-70IND+	IC NVSRAM 64KBIT 70NS 28DIP

鐩搁棞(gu膩n)PDF璩囨枡

PDF鎻忚堪

AGM36DTBD

CONN EDGECARD 72POS R/A .156 SLD

EP1S30F1020C7

IC STRATIX FPGA 30K LE 1020-FBGA

DS1230YP-70IND+

IC NVSRAM 256KBIT 70NS 34PCM

EP1SGX25DF1020C7

IC STRATIX GX FPGA 25K 1020-FBGA

DS1225AB-70IND+

IC NVSRAM 64KBIT 70NS 28DIP

鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉)	鍙冩暩(sh霉)鎻忚堪
EP2S60F1020I4	鍔熻兘鎻忚堪:FPGA - 鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄ｅ垪 FPGA - Stratix II 3022 LABs 718 IOs RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁�(sh霉)閲�: 閭忚集濉婃暩(sh霉)閲�:943 鍏�(n猫i)宓屽紡濉奟AM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-256
EP2S60F1020I4N	鍔熻兘鎻忚堪:FPGA - 鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄ｅ垪 FPGA - Stratix II 3022 LABs 718 IOs RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁�(sh霉)閲�: 閭忚集濉婃暩(sh霉)閲�:943 鍏�(n猫i)宓屽紡濉奟AM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-256
EP2S60F484C3	鍔熻兘鎻忚堪:FPGA - 鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄ｅ垪 FPGA - Stratix II 3022 LABs 334 IOs RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁�(sh霉)閲�: 閭忚集濉婃暩(sh霉)閲�:943 鍏�(n猫i)宓屽紡濉奟AM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-256
EP2S60F484C3N	鍔熻兘鎻忚堪:FPGA - 鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄ｅ垪 FPGA - Stratix II 3022 LABs 334 IOs RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁�(sh霉)閲�: 閭忚集濉婃暩(sh霉)閲�:943 鍏�(n猫i)宓屽紡濉奟AM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-256
EP2S60F484C4	鍔熻兘鎻忚堪:FPGA - 鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄ｅ垪 FPGA - Stratix II 3022 LABs 334 IOs RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁�(sh霉)閲�: 閭忚集濉婃暩(sh霉)閲�:943 鍏�(n猫i)宓屽紡濉奟AM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-256

鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉)

鍙冩暩(sh霉)鎻忚堪

EP2S60F1020I4

鍔熻兘鎻忚堪:FPGA - 鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄ｅ垪 FPGA - Stratix II 3022 LABs 718 IOs RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁�(sh霉)閲�: 閭忚集濉婃暩(sh霉)閲�:943 鍏�(n猫i)宓屽紡濉奟AM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-256

EP2S60F1020I4N

EP2S60F484C3

鍔熻兘鎻忚堪:FPGA - 鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄ｅ垪 FPGA - Stratix II 3022 LABs 334 IOs RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁�(sh霉)閲�: 閭忚集濉婃暩(sh霉)閲�:943 鍏�(n猫i)宓屽紡濉奟AM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-256

EP2S60F484C3N

EP2S60F484C4

閲囪臣闇€姹�

(鑻ュ彧閲囪臣涓€姊濆瀷铏�锛屽～瀵竴琛屽嵆鍙�)

*鍨嬭櫉	*鏁�(sh霉)閲�	寤犲晢	鎵硅櫉	灏佽

娣诲姞鏇村閲囪臣

鍨嬭櫉锛�	EP2S60F1020C5N
寤犲晢锛�	Altera
鏂囦欢闋佹暩(sh霉)锛�	118/768闋�
鏂囦欢澶�?銆�?/td>	0K
鎻忚堪锛�	IC STRATIX II FPGA 60K 1020-FBGA
鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛�	Three Reasons to Use FPGA's in Industrial Designs
妯�(bi膩o)婧�(zh菙n)鍖呰锛�	6
绯诲垪锛�	Stratix® II
LAB/CLB鏁�(sh霉)锛�	3022
閭忚集鍏冧欢/鍠厓鏁�(sh霉)锛�	60440
RAM 浣嶇附瑷堬細	2544192
杓稿叆/杓稿嚭鏁�(sh霉)锛�	718
闆绘簮闆诲锛�	1.15 V ~ 1.25 V
瀹夎椤炲瀷锛�	琛ㄩ潰璨艰
宸ヤ綔婧害锛�	0°C ~ 85°C
灏佽/澶栨锛�	1020-BBGA
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細	1020-FBGA锛�33x33锛�
閰嶇敤锛�	544-1700-ND - DSP KIT W/STRATIX II EP2S60N 544-1697-ND - NIOS II KIT W/STRATIX II EP2S60N
鍏跺畠鍚嶇ū锛�	544-1902 EP2S60F1020C5N-ND

閲囪臣闇€姹�

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鎴戠殑鑱�(li谩n)绯绘柟寮�

閲囪臣闇€姹�

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鎴戠殑鑱�(li谩n)绯绘柟寮�

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