2–88
Altera Corporation
Stratix II Device Handbook, Volume 1
May 2007
I/O Structure
Figure 2–57. Stratix II I/O Banks
(1)
Figure 2–57 is a top view of the silicon die that corresponds to a reverse view for flip-chip packages. It is a graphical
representation only.
(2)
Depending on the size of the device, different device members have different numbers of VREF groups. Refer to the
pin list and the Quartus II software for exact locations.
(3)
Banks 9 through 12 are enhanced PLL external clock output banks. These PLL banks utilize the adjacent VREF group
when voltage-referenced standards are implemented. For example, if an SSTL input is implemented in PLL bank
10, the voltage level at VREFB7 is the reference voltage level for the SSTL input.
(4)
Horizontal I/O banks feature SERDES and DPA circuitry for high speed differential I/O standards. See the High
Speed Differential I/O Interfaces in Stratix II & Stratix II GX Devices chapter of the Stratix II Device Handbook, Volume 2
or the Stratix II GX Device Handbook, Volume 2 for more information on differential I/O standards.
Bank 3
Bank 4
Bank 11
Bank 9
PLL11
PLL5
PLL7
PLL1
PLL2
PLL4
PLL3
PLL10
I/O banks 7, 8, 10 & 12 support all
single-ended I/O standards and
differential I/O standards except for
HyperTransport technology for
both input and output operations.
I/O banks 3, 4, 9 & 11 support all
single-ended I/O standards and
differential I/O standards except for
HyperTransport technology for
both input and output operations.
VREF0B3
VREF1B3
VREF2B3
VREF3B3
VREF4B3
VREF0B4
VREF1B4
VREF2B4
VREF3B4
VREF4B4
Bank 8
Bank 7
Bank 12
Bank 10
PLL12
PLL6
PLL8
PLL9
VREF4B8
VREF3B8
VREF2B8
VREF1B8
VREF0B8
VREF4B7
VREF3B7
VREF2B7
VREF1B7
VREF0B7
VR
EF
3
B
2
VR
EF
2
B
2
VR
EF
1
B
2
VR
EF
0
B
2
Ba
nk
2
VR
EF
3
B
1
VR
EF
2
B
1
VR
EF
1
B
1
VR
EF
0
B
1
Ba
n
k1
VR
EF
1
B
5
VR
EF
2
B
5
VR
EF
3
B
5
VR
EF
4
B
5
Ba
nk
5
VR
EF
1
B
6
VR
EF
2
B
6
VR
EF
3
B
6
VR
EF
4
B
6
Ba
n
k6
VR
EF
4
B
2
VR
EF
0
B
5
VR
EF
4
B
1
VR
EF
0
B
6
DQS4T
DQS3T
DQS2T
DQS1T
DQS0T
DQS4B
DQS3B
DQS2B
DQS1B
DQS0B
DQS8B
DQS7B
DQS6B
DQS5B
DQS8T
DQS7T
DQS6T
DQS5T
This I/O bank supports LVDS
and LVPECL standards for input
clock operations. Differential
HSTL and differential SSTL
standards are supported for both
input and output operations.
This I/O bank supports LVDS
and LVPECL standards for input
clock operations. Differential
HSTL and differential SSTL
standards are supported for both
input and output operations.
This I/O bank supports LVDS
and LVPECL standards for input
clock operations. Differential
HSTL and differential SSTL
standards are supported for both
input and output operations.
This I/O bank supports LVDS
and LVPECL standards for input
clock operations. Differential
HSTL and differential SSTL
standards are supported for both
input and output operations.
I/O banks 1, 2, 5 & 6 support LVTTL, LVCMOS,
2.5-V, 1.8-V, 1.5-V, SSTL-2, SSTL-18 Class I,
HSTL-18 Class I, HSTL-15 Class I, LVDS, and
HyperTransport standards for input and output
operations. HSTL-18 Class II, HSTL-15-Class II,
SSTL-18 Class II standards are only supported
for input operations.