Altera Corporation
2–27
May 2007
Stratix II Device Handbook, Volume 1
Stratix II Architecture
C16 column interconnects span a length of 16 LABs and provide the
fastest resource for long column connections between LABs, TriMatrix
memory blocks, DSP blocks, and IOEs. C16 interconnects can cross
M-RAM blocks and also drive to row and column interconnects at every
fourth LAB. C16 interconnects drive LAB local interconnects via C4 and
R4 interconnects and do not drive LAB local interconnects directly.
All embedded blocks communicate with the logic array similar to LAB-
to-LAB interfaces. Each block (that is, TriMatrix memory and DSP blocks)
connects to row and column interconnects and has local interconnect
regions driven by row and column interconnects. These blocks also have
direct link interconnects for fast connections to and from a neighboring
LAB. All blocks are fed by the row LAB clocks, labclk[5..0].
Table 2–2 shows the Stratix II device’s routing scheme.
Table 2–2. Stratix II Device Routing Scheme (Part 1 of 2)
Source
Destination
Shared
Arithmetic
Chain
Carr
yChain
Reg
ister
Chain
Local
Intercon
nect
Direct
Link
Inter
connect
R4
Interconnect
R24
Inter
connect
C4
In
terconnect
C16
Inte
rconn
ect
AL
M
M512
RAM
Block
M4K
RA
M
Bl
ock
M-R
A
M
Bl
ock
DSP
Block
s
Colum
n
IOE
Row
IO
E
Shared arithmetic chain
v
Carry chain
v
Register chain
v
Local interconnect
vvvvvvv
Direct link interconnect
v
R4 interconnect
v
vvvv
R24 interconnect
vvvv
C4 interconnect
vvv
C16 interconnect
vvvv
ALM
vvvvvv
v
M512 RAM block
vvv
v
M4K RAM block
vvv
v
M-RAM block
vvvv
DSP blocks
vv
v
