
Altera Corporation
1–85
July 2009
Stratix II Device Handbook, Volume 2
PLLs in Stratix II and Stratix II GX Devices
Figure 1–50. Stratix II Corner Fast PLLs, Clock Pin and Logic Array Signal
Connectivity to Global and Regional Clock Networks
(1)
The corner FPLLs can also be driven through the global or regional clock networks.
The global or regional clock input can be driven by an output from another PLL, a
pin-driven dedicated global or regional clock, or through a clock control block,
provided the clock control block is fed by an output from another PLL or a
pin-driven dedicated global or regional clock. An internally generated global
signal cannot drive the PLL.
C0
C1
C2
C3
F
ast
PLL
7
RCK0
RCK2
RCK1
RCK3
GCK0
GCK2
GCK9
GCK11
GCK1
GCK3
GCK8
GCK10
RCK4
RCK6
RCK5
RCK7
RCK17
RCK16
RCK18
RCK19
RCK21
RCK23
RCK20
RCK22
C0
C1
C2
C3
F
ast
PLL
8
C0
C1
C2
C3
F
ast
PLL
10
C0
C1
C2
C3
F
ast
PLL
9
FPLL7CLK
FPLL
8CLK
FPLL10CL
K
FPLL
9CL
K