參數(shù)資料
型號： DS33ZH11+
廠商： Maxim Integrated Products
文件頁數(shù)： 83/172頁
文件大小： 0K
描述： IC MAPPER ETHERNET 100CSBGA
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 7
應(yīng)用： 數(shù)據(jù)傳輸
接口： 串行
電源電壓： 1.8V，2.5V，3.3V
封裝/外殼： 100-LFBGA，CSPBGA
供應(yīng)商設(shè)備封裝： 100-CSBGA（10x10）
包裝： 托盤
安裝類型： 表面貼裝
DS33Z11 Ethernet Mapper
18 of 172
NAME
PIN #
DS33Z11
CSBGA
(169)
PIN #
DS33ZH1
1
BGA(100)
TYPE
FUNCTION
RDEN/
RBSYNC
H2
—
I
Receive Data Enable: The receive data enable is
programmable to block the receive data. The RDEN must
be coincident with the RSER data bit to be blocked or
enabled. The active polarity of RDEN is programmable in
register LI.RSLCR. It is recommended for both T1/E1 and
T3/E3 applications that use gapped clocks. The RDEN
signal is provided for interfacing to framers that do not
have a gapped clock facility.
Receive Byte Synchronization Input: Provides byte
synchronization input to X.86 decoder. This signal will go
high at the first bit of the byte as it arrives. This signal can
occur at maximum rate every 8 bits. Note that a long as
the Z11 receives one RBSYNC indicator. The X.86
receiver will determine the byte boundary. Hence the Z11
does not require a continuous 8-bit sync indicator. A new
sync pulse is required if the byte boundary changes.
Note that while in Hardware mode with HDLC (non X.86)
operation, this pin must be tied high.
MII/RMII PORT
REF_CLK
D13
—
I
Reference Clock (RMII and MII): When in RMII mode, all
signals from the PHY are synchronous to this clock input
for both transmit and receive. This required clock can be
up to 50 MHz and should have ±100 ppm accuracy.
When in MII mode in DCE operation, the DS33Z11 uses
this input to generate the RX_CLK and TX_CLK outputs
as required for the Ethernet PHY interface. When the MII
interface is used with DTE operation, this clock is not
required and should be tied low.
In DCE and RMII modes, this input must have a stable
clock input before setting the RST pin high for normal
operation.
REF_CLKO
E13
G10
O
Reference Clock Output (RMII and MII): A derived clock
output up to 50 MHz, generated by internal division of the
SYSCLKI signal. Frequency accuracy of the REF_CLKO
signal will be proportional to the accuracy of the user-
supplied SYSCLKI signal. See Section 8.3.2 for more
information.
TX_CLK
A8
A6
IO
Transmit Clock (MII): Timing reference for TX_EN and
TXD[3:0]. The TX_CLK frequency is 25 MHz for 100 Mbps
operation and 2.5 MHz for 10 Mbps operation.
In DTE mode, this is a clock input provided by the PHY. In
DCE mode, this is an output derived from REF_CLK
providing 2.5 MHz (10 Mbps operation) or 25 MHz (100
Mbps operation).
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