參數(shù)資料
型號: DS33ZH11+
廠商: Maxim Integrated Products
文件頁數(shù): 155/172頁
文件大?。?/td> 0K
描述: IC MAPPER ETHERNET 100CSBGA
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 7
應(yīng)用: 數(shù)據(jù)傳輸
接口: 串行
電源電壓: 1.8V,2.5V,3.3V
封裝/外殼: 100-LFBGA,CSPBGA
供應(yīng)商設(shè)備封裝: 100-CSBGA(10x10)
包裝: 托盤
安裝類型: 表面貼裝
DS33Z11 Ethernet Mapper
83 of 172
9.3 Arbiter Registers
The Arbiter manages the transport between the Ethernet port and the Serial Interface. It is responsible for
queuing and dequeuing data to an external SDRAM. The arbiter handles requests from the HDLC and MAC to
transfer data to/from the SDRAM. The base address of the Arbiter register space is 0040h.
9.3.1 Arbiter Register Bit Descriptions
Register Name:
AR.RQSC1
Register Description:
Arbiter Receive Queue Size Connection
Register Address:
40h
Bit #
7
6
5
4
3
2
1
0
Name
RQSC7
RQSC6
RQSC5
RQSC4
RQSC3
RQSC2
RQSC1
RQSC0
Default
0
1
0
1
Bits 0-7: Receive Queue Size (RQSC[0:7]) These 7 bits of the size of receive queue associated with the
connection. Receive queue is for data arriving from the MAC to be sent to the WAN. The Queue address size is
defined in increments of 32 x 2048 bytes. The queue size is AR.RQSC1 multiplied by 32 to determine the number
of 2048 byte packets that can be stored in the queue. This queue is constructed in the external SDRAM. Note:
Queue size of 0 is not allowed and should never be set.
Register Name:
AR.TQSC1
Register Description:
Arbiter Transmit Queue Size Connection 1
Register Address:
41h
Bit #
7
6
5
4
3
2
1
0
Name
TQSC7
TQSC6
TQSC5
TQSC4
TQSC3
TQSC2
TQSC1
TQSC0
Default
0
1
Bits 0-7: Transmit Queue Size (TQSC[0:7]) This is size of transmit queue associated with the connection. The
queue address size is defined in increments of 32 packets. The range of bytes will depend on the external
SDRAM connected to the DS33Z11. Transmit queue is the data queue for data arriving on the WAN that is sent
to the MAC. Note that queue size of 0 is not allowed and should never be set.
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