參數(shù)資料
型號： DS33ZH11+
廠商： Maxim Integrated Products
文件頁數(shù)： 152/172頁
文件大?。?/td> 0K
描述： IC MAPPER ETHERNET 100CSBGA
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 7
應(yīng)用： 數(shù)據(jù)傳輸
接口： 串行
電源電壓： 1.8V，2.5V，3.3V
封裝/外殼： 100-LFBGA，CSPBGA
供應(yīng)商設(shè)備封裝： 100-CSBGA（10x10）
包裝： 托盤
安裝類型： 表面貼裝
DS33Z11 Ethernet Mapper
80 of 172
Register Name:
GL.C1QPR
Register Description:
Connection 1 Queue Pointer Reset
Register Address:
12h
Bit #
7
6
5
4
3
2
1
0
Name
-
C1MRPRR
C1HWPRR
C1MHPR
C1HRPR
Default
0
Bit 3: MAC Read Pointer Reset (C1MRPR) Setting this bit to 1 resets the receive queue read pointer for
connection 1. This queue pointer must be reset after a disconnect and before a connection. The user must clear
the bit before subsequent reset operations.
Bit 2: HDLC Write Pointer Reset (C1HWPR) Setting this bit to 1 resets the receive queue write pointer for
connection 1. This queue pointer must be reset after a disconnect and before a connection. The user must clear
the bit before subsequent reset operations.
Bit 1: HDLC Read Pointer Reset (C1MHPR) Setting this bit to 1 resets the transmit queue read pointer for
connection 1. This queue pointer must be reset after a disconnect and before a connection. The user must clear
the bit before subsequent reset operations.
Bit 0: MAC Transmit Write Pointer Reset (C1HRPR) Setting this bit to 1 resets the transmit queue write pointer
for connection 1. This queue pointer must be reset after a disconnect and before a connection. The user must
clear the bit before subsequent reset operations.
Register Name:
GL.BISTEN
Register Description:
BIST Enable
Register Address:
20h
Bit #
7
6
5
4
3
2
1
0
Name
-
BISTE
Default
0
Bit 0: BIST Enable (BISTE) If this bit is set the DS33Z11 performs BIST test on the SDRAM. Normal data
communication is halted while BIST enable is high. The user must reset the DS33Z11 after completion of BIST
test before normal dataflow can begin.
Register Name:
GL.BISTPF
Register Description:
BIST PassFail
Register Address:
21h
Bit #
7
6
5
4
3
2
1
0
Name
-
BISTDN
BISTPF
Default
0
Bit 1: BIST DONE (BISTDN) If this bit is set to 1, the DS33Z11 has completed the BIST Test initiated by BISTE.
The pass fail result is available in BISTPF.
Bit 0: BIST PassFail (BISTPF) This bit is equal to 0 after the DS33Z11 performs BIST testing on the SDRAM
and the test passes. This bit is set to 1 if the test failed. This bit is valid only after the BIST test is complete and
the BIST DN bit is set. If set this bit can only be cleared by resetting the DS33Z11.
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