參數(shù)資料
型號： DS33ZH11+
廠商： Maxim Integrated Products
文件頁數(shù)： 17/172頁
文件大小： 0K
描述： IC MAPPER ETHERNET 100CSBGA
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 7
應(yīng)用： 數(shù)據(jù)傳輸
接口： 串行
電源電壓： 1.8V，2.5V，3.3V
封裝/外殼： 100-LFBGA，CSPBGA
供應(yīng)商設(shè)備封裝： 100-CSBGA（10x10）
包裝： 托盤
安裝類型： 表面貼裝
DS33Z11 Ethernet Mapper
113 of 172
Register Name:
LI.TQHT
Register Description:
Serial Interface Transmit Queue High Threshold (Watermark)
Register Address:
125h
Bit #
7
6
5
4
3
2
1
0
Name
TQHT7
TQHT6
TQHT5
TQHT4
TQHT3
TQHT2
TQHT1
TQHT0
Default
0
Bits 0 – 7: Transmit Queue High Threshold (TQHT[0:7]) The transmit queue high threshold for the connection,
in increments of 32 packets of 2048 bytes each. The value of this register is multiplied by 32 * 2048 bytes to
determine the byte location of the threshold. Note that the transmit queue is for data that was received from the
Serial Interface to be sent to the Ethernet Interface.
Register Name:
LI.TQTIE
Register Description:
Serial Interface Transmit Queue Cross Threshold Interrupt Enable
Register Address:
126h
Bit #
7
6
5
4
3
2
1
0
Name
-
TFOVFIE
TQOVFIE
TQHTIE
TQLTIE
Default
0
Bit 3: Transmit FIFO Overflow for Connection Interrupt Enable (TFOVFIE) If this bit is set, the watermark
interrupt is enabled for TFOVFLS.
Bit 2: Transmit Queue Overflow for Connection Interrupt Enable (TQOVFIE) If this bit is set, the watermark
interrupt is enabled for TQOVFLS.
Bit 1: Transmit Queue for Connection High Threshold Interrupt Enable (TQHTIE) If this bit is set, the
watermark interrupt is enabled for TQHTS.
Bit 0: Transmit Queue for Connection Low Threshold Interrupt Enable (TQLTIE) If this bit is set, the
watermark interrupt is enabled for TQLTS.
Register Name:
LI.TQCTLS
Register Description:
Serial Interface Transmit Queue Cross Threshold Latched Status
Register Address:
127h
Bit #
7
6
5
4
3
2
1
0
Name
-
TFOVFLS
TQOVFLS
TQHTLS
TQLTLS
Default
-
Bit 3: Transmit Queue FIFO Overflowed Latched Status (TFOVFLS) This bit is set if the transmit queue FIFO
has overflowed. This register is cleared after a read. This FIFO is for data to be transmitted from the HDLC to be
sent to the SDRAM.
Bit 2: Transmit Queue Overflow Latched Status (TQOVFLS) This bit is set if the transmit queue has
overflowed. This register is cleared after a read.
Bit 1: Transmit Queue for Connection Exceeded High Threshold Latched Status (TQHTLS) This bit is set if
the transmit queue crosses the High Watermark. This register is cleared after a read.
Bit 0: Transmit Queue for Connection Exceeded Low Threshold Latched Status (TQLTLS) This bit is set if
the transmit queue crosses the Low Watermark. This register is cleared after a read.
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