參數(shù)資料
型號： DS33ZH11+
廠商： Maxim Integrated Products
文件頁數(shù)： 165/172頁
文件大?。?/td> 0K
描述： IC MAPPER ETHERNET 100CSBGA
產(chǎn)品培訓模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝： 7
應用： 數(shù)據(jù)傳輸
接口： 串行
電源電壓： 1.8V，2.5V，3.3V
封裝/外殼： 100-LFBGA，CSPBGA
供應商設備封裝： 100-CSBGA（10x10）
包裝： 托盤
安裝類型： 表面貼裝
DS33Z11 Ethernet Mapper
92 of 172
Register Name:
LI.LPBK
Register Description:
Serial Interface Loopback Control Register
Register Address:
0C2h
Bit #
7
6
5
4
3
2
1
0
Name
-
QLP
Default
0
Bit 0: Queue Loopback Enable (QLP) If this bit set to 1, data received on the Serial Interface is looped back to
the Serial Interface transmitter. Received data will not be sent from the Serial Interface to the Ethernet Interface.
Buffered packet data will remain in queue until the loopback is removed.
9.5.3
Transmit HDLC Processor Registers
Register Name:
LI.TPPCL
Register Description:
Transmit Packet Processor Control Low Register
Register Address:
0C4h
Bit #
7
6
5
4
3
2
1
0
Name
-
TFAD
TF16
TIFV
TSD
TBRE
TIAEI
Default
0
Note: The user should take care not to modify this register value during packet error insertion.
Bits 5 - 6: Transmit FCS Append Disable (TFAD) – This bit controls whether or not an FCS is appended to the
end of each packet. When equal to 0, the calculated FCS bytes are appended to packets. When set to 1, packets
are transmitted without FCS. In X.86 Mode, FCS is always 32 bits and is always appended to the packet.
Bit 4: Transmit FCS-16 Enable (TF16) – When 0, the FCS processing uses a 32-bit FCS. When 1, the FCS
processing uses a 16-bit FCS. In X.86 Mode, 32-bit FCS processing is enabled.
Bit 3: Transmit Bit Synchronous Inter-frame Fill Value (TIFV) – When 0, inter-frame fill is done with the flag
sequence (7Eh). When 1, inter-frame fill is done with all '1's. This bit is ignored in byte synchronous mode. In X.86
mode the interframe flag is always 7E.
Bit 2: Transmit Scrambling Disable (TSD) – When equal to 0, X
43+1 scrambling is performed. When set to 1,
scrambling is disabled. Note that in hardware mode, transmit scrambling is controlled by the SCD hardware pin.
Bit 1: Transmit Bit Reordering Enable (TBRE) – When equal to 0, bit reordering is disabled (The first bit
transmitted is from the MSB of the transmit FIFO byte TFD [7]). When set to 1, bit reordering is enabled (The first
bit transmitted is from the LSB of the transmit FIFO byte TFD [0]). Note that this function can be controlled in
Hardware mode with the BREO hardware pin.
Bit 0: Transmit Initiate Automatic Error Insertion (TIAEI) – This write-only bit initiates error insertion. See the
LI.TEPHC register definition for details of usage.
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