參數(shù)資料
型號： DS3112
英文描述： RECT BRIDGE GPP 15A 400V GBJ
中文描述： TEMPE T3/E3復(fù)用器、3.3V T3/E3成幀器及M13/E13/G.747復(fù)用器
文件頁數(shù)： 94/135頁
文件大小： 585K
代理商： DS3112
DS3112
94 of 135
Note 2:
Packets with three or fewer bytes (including the CRC FCS) in between flags are invalid and the
data that appears in the FIFO in such instances is meaningless. If only one byte is received between flags,
then both the CBYTE and OBYTE bits will be set. If two bytes are received, then OBYTE will be set for
the first one received and CBYTE will be set for the second byte received. If three bytes are received,
then OBYTE will be set for the first one received and CBYTE will be set for the third byte received. In
all of these cases, the packet status will be reported as PS0 = 0 / PS1 = 1 and the data in the FIFO should
be ignored.
Bits 0 to 7/Receive FIFO Data (D0 to D7).
Data from the Receive FIFO can be read from these bits. D0
is the LSB and is received first while D7 is the MSB and is received last.
Bit 8/Opening Byte (OBYTE).
This bit will be set to a one when the byte available at the D0 to D7 bits
from the Receive FIFO is the first byte of a HDLC packet.
Bit 9/Closing Byte (CBYTE).
This bit will be set to a one when the byte available at the D0 to D7 bits
from the Receive FIFO is the last byte of a HDLC packet whether the packet is valid or not. The host can
use the PS0 and PS1 bits to determine if the packet is valid or not.
Bits 10 and 11/Packet Status Bits 0 and 1 (PS0 and PS1).
These bits are only valid when the CBYTE
bit is set to a one. These bits inform the host of the validity of the incoming packet and the cause of the
problem if the packet was received in error.
PACKET
STATUS
0
0
Valid
0
1
Invalid
Corrupt CRC
1
0
Invalid
Incoming packet was either too short (three or fewer bytes including
the CRC) or did not contain an integral number of octets
1
1
Invalid
Abort sequence detected
Register Name:
THDLC
Register Description:
Transmit HDLC FIFO
Register Address:
84h
Bit #
7
6
5
4
Name
D7
D6
D5
D4
Default
0
0
0
0
Bit #
15
14
13
12
Name
n/a
n/a
n/a
n/a
Default
-
-
-
-
PS1
PS0
REASON FOR INVALID RECEPTION OF THE PACKET
3
2
1
0
D3
0
D2
0
D1
0
D0
0
11
n/a
-
10
n/a
-
9
8
n/a
-
TMEND
0
相關(guān)PDF資料
PDF描述
DS3112N RECT BRIDGE GPP 15A 600V GBJ
DS3112RD RECT BRIDGE GPP 15A 800V GBJ
DS3134 Chateau Channelized T1 And E1 And HDLC Controller
DS3160 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
DS3171 Single/Dual/Triple/Quad DS3/E3 Single-Chip Transceivers
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DS3112+ 功能描述:網(wǎng)絡(luò)控制器與處理器 IC TEMPE T3/E3 MUX FRMR & M13/E13/G.747 MUX RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS3112+W 功能描述:網(wǎng)絡(luò)控制器與處理器 IC TEMPE T3/E3 MUX FRMR & M13/E13/G.747 MUX RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS3112D1 功能描述:網(wǎng)絡(luò)控制器與處理器 IC TEMPE T3/E3 MUX FRMR & M13/E13/G.747 MUX RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS3112D1+ 功能描述:網(wǎng)絡(luò)控制器與處理器 IC TEMPE T3/E3 MUX FRMR & M13/E13/G.747 MUX RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS3112DK 功能描述:網(wǎng)絡(luò)開發(fā)工具 DS3112 Dev Kit RoHS:否 制造商:Rabbit Semiconductor 產(chǎn)品:Development Kits 類型:Ethernet to Wi-Fi Bridges 工具用于評估:RCM6600W 數(shù)據(jù)速率:20 Mbps, 40 Mbps 接口類型:802.11 b/g, Ethernet 工作電源電壓:3.3 V
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*