- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄376975 > DS3112 RECT BRIDGE GPP 15A 400V GBJ PDF資料下載
參數(shù)資料
| 型號(hào)： | DS3112 |
| 英文描述： | RECT BRIDGE GPP 15A 400V GBJ |
| 中文描述： | TEMPE T3/E3復(fù)用器、3.3V T3/E3成幀器及M13/E13/G.747復(fù)用器 |
| 文件頁(yè)數(shù)： | 39/135頁(yè) |
| 文件大?。?/td> | 585K |
| 代理商： | DS3112 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)當(dāng)前第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)
DS3112
39 of 135
Bit 2/Change in BERT Status (BERT).
This read-only real-time status bit will be set to a one if there is
a major change of status in the BERT receiver and the associated interrupt enable bit is set in the
BERTCO register. A major change of status is defined as either a change in the receive synchronization
(i.e., the BERT has gone into or out of receive synchronization), a bit error has been detected, or an
overflow has occurred in either the Bit Counter or the Error Counter. The host must read the status bits of
the BERT in the BERT Status Register (BERTEC0) to determine the change of state. This bit will be
cleared when the BERTEC0 is read and will not be set again until the BERT has experienced another
change of state. The setting of this status bit can cause a hardware interrupt to occur if the BERT bit in
the Interrupt Mask for MSR (IMSR) register is set to a one. The interrupt will be allowed to clear when
the BERTEC0 register is read (Figure 4.3D).
Bit 3/Change in HDLC Status (HDLC).
This read-only real-time status bit will be set to a one if there is
a change of status in the HDLC controller and the associated interrupt enable bit is set in the IHSR
register. The host must read the status bits of the HDLC in the HDLC Status Register (HSR) to determine
the change of state. This bit will be cleared when the HSR is read and will not be set again until the
HDLC has experienced another change of state. The setting of this status bit can cause a hardware
interrupt to occur if the HDLC bit in the Interrupt Mask for MSR (IMSR) register is set to a one. The
interrupt will be allowed to clear when the HSR register is read (Figure 4.3E).
Bit 4/Change in FEAC Status (FEAC).
This read-only real-time status bit will be set to a one when the
FEAC controller has detected and verified a new Far End Alarm and Control (FEAC) 16-bit code word.
This bit will be cleared when the FEAC Status Register (FSR) is read and will not be set again until the
FEAC controller has detected and verified another new code word. The setting of this status bit can cause
a hardware interrupt to occur if the FEAC bit in the Interrupt Mask for MSR (IMSR) register is set to a
one. The interrupt will be allowed to clear when the FSR register is read.
Bit 5/Change in T2/E2 LOF or AIS Status (T2E2SR1).
This read-only real-time status bit will be set to
a one when one or more of the T2/E2/G.747 framers have detected a change in either Loss Of Frame
(LOF) or Alarm Indication Signal (AIS) and the associated interrupt enable bit is set in the T2E2SR1
register. See the T2E2SR1 register description in Section 6.3 for more details. This bit will be cleared
when the T2E2SR1 register is read. The setting of this status bit can cause a hardware interrupt to occur if
the T2E2SR1 bit in the Interrupt Mask for MSR (IMSR) register is set to a one. The interrupt will be
allowed to clear when the T2E2SR1 register is read (Figure 4.3F).
Bit 6/Change in T2/E2 RAI Status (T2E2SR2).
This read-only real-time status bit will be set to a one
when one or more of the T2/E2/G.747 framers have detected a change in the detection of the Remote
Alarm Indication (RAI) signal and the interrupt enable (bit 7) is set in the T2E2SR2 register. See the
T2E2SR2 register description in Section 6.3 for more details. This bit will be cleared when the T2E2SR2
register is read. The setting of this status bit can cause a hardware interrupt to occur if the T2E2SR2 bit in
the Interrupt Mask for MSR (IMSR) register is set to a one. The interrupt will be allowed to clear when
the T2E2SR2 register is read (Figure 4.3G).
Bit 8/T1 Loopback Detected (T1LB).
This read-only real-time status bit will be set to a one when one or
more of the T2 framers have detects an active T1 loopback command. See the T1LBSR1 and T1LBSR2
register descriptions in Section 7.3 for more details. This bit will be cleared when the T1 loopback
command is no longer active on any of the lines. The setting of this status bit can cause a hardware
interrupt to occur if the T1LB bit in the Interrupt Mask for MSR (IMSR) register is set to a one. The
interrupt will be allowed to clear when the none of the T2 framers detects an active T1 loopback
command (Figure 4.3H).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DS3112N | RECT BRIDGE GPP 15A 600V GBJ |
| DS3112RD | RECT BRIDGE GPP 15A 800V GBJ |
| DS3134 | Chateau Channelized T1 And E1 And HDLC Controller |
| DS3160 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| DS3171 | Single/Dual/Triple/Quad DS3/E3 Single-Chip Transceivers |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS3112+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC TEMPE T3/E3 MUX FRMR & M13/E13/G.747 MUX RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS3112+W | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC TEMPE T3/E3 MUX FRMR & M13/E13/G.747 MUX RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS3112D1 | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC TEMPE T3/E3 MUX FRMR & M13/E13/G.747 MUX RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS3112D1+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC TEMPE T3/E3 MUX FRMR & M13/E13/G.747 MUX RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS3112DK | 功能描述:網(wǎng)絡(luò)開發(fā)工具 DS3112 Dev Kit RoHS:否 制造商:Rabbit Semiconductor 產(chǎn)品:Development Kits 類型:Ethernet to Wi-Fi Bridges 工具用于評(píng)估:RCM6600W 數(shù)據(jù)速率:20 Mbps, 40 Mbps 接口類型:802.11 b/g, Ethernet 工作電源電壓:3.3 V |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。