- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄376975 > DS3112 RECT BRIDGE GPP 15A 400V GBJ PDF資料下載
參數(shù)資料
| 型號： | DS3112 |
| 英文描述： | RECT BRIDGE GPP 15A 400V GBJ |
| 中文描述： | TEMPE T3/E3復用器、3.3V T3/E3成幀器及M13/E13/G.747復用器 |
| 文件頁數(shù)： | 40/135頁 |
| 文件大小： | 585K |
| 代理商： | DS3112 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁當前第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁
DS3112
40 of 135
Bit 9/Change in T3/E3 Framer Status (T3E3SR).
This read-only real-time status bit will be set to a one
when the T3/E3 framer has detected a change in RAI, AIS, LOF, LOS, or T3 Idle signal or has detected
the start of a Transmit or Receive Frame and the associated interrupt enable bit is set in the T3E3SR
register. See the T3E3SR register description in Section 5.3 for more details. This bit will be cleared
when the T3E3SR register is read. The setting of this status bit can cause a hardware interrupt to occur if
the T3E3SR bit in the Interrupt Mask for MSR (IMSR) register is set to a one. The interrupt will be
allowed to clear when the T3E3SR register is read (Figure 4.3I).
Bit 10/Loss Of Transmit Clock Detected (LOTC).
This read-only real-time status bit will be set to a
one when the device detects that the FTCLK clock has not toggled for 200ns (±100ns). This bit will be
cleared when a clock is detected at the FTCLK input. The setting of this status bit can cause a hardware
interrupt to occur if the LOTC bit in the Interrupt Mask for MSR (IMSR) register is set to a one. The
interrupt will be allowed to clear when the device detects a clock at FTCLK. The HRCLK checks for the
presence of the FTCLK. On reset, both the LOTC and LORC status bits will be set and then immediately
cleared if the clock is present.
Bit 11/Loss Of Receive Clock Detected (LORC).
This read-only real-time status bit will be set to a one
when the device detects that the HRCLK clock has not toggled for 200ns (±100ns). This bit will be
cleared when a clock is detected at the HRCLK input. The setting of this status bit can cause a hardware
interrupt to occur if the LORC bit in the Interrupt Mask for MSR (IMSR) register is set to a one. The
interrupt will be allowed to clear when the device detects a clock at HRCLK. The FTCLK checks for the
presence of the HRCLK. On reset, both the LOTC and LORC status bits will be set and then immediately
cleared if the clock is present.
Bit 12/State of the T3E3MS Input Signal (T3E3MS).
This read-only real-time status bit reflects the
current state of the external T3E3MS input signal. This status bit cannot generate an interrupt.
Bit 13/State of the G.747E Input Signal (G.747E).
This read-only real-time status bit reflects the
current state of the external G.747E input signal. This status bit cannot generate an interrupt.
BERT STATUS BIT FLOW
Figure 4.3D
Note:
All event and alarm latches above are cleared when the BERTEC0 register is read.
Alarm Latch
Change in State Detect
RLOS
(BERTEC0
Bit 4)
Internal RLOS
Signal from
BERT
Event Latch
Internal Bit
Error Detected
Signal from
BERT
Event Latch
Internal Counter
Overflow
Signal from
BERT
OR
BED
(BERTEC0
Bit 3)
BECO or BBCO
(BERTEC0
Bits 1 & 2)
Mask
BERT
(IMSR Bit 2)
INT*
Hardware
Signal
BERT
Status Bit
(MSR Bit 2)
Mask
IESYNC (BERTC0 Bit 15)
Mask
Mask
IEBED (BERTC0 Bit 14)
IEOF (BERTC0 Bit 13)
Event Latch
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DS3112N | RECT BRIDGE GPP 15A 600V GBJ |
| DS3112RD | RECT BRIDGE GPP 15A 800V GBJ |
| DS3134 | Chateau Channelized T1 And E1 And HDLC Controller |
| DS3160 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| DS3171 | Single/Dual/Triple/Quad DS3/E3 Single-Chip Transceivers |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS3112+ | 功能描述:網(wǎng)絡控制器與處理器 IC TEMPE T3/E3 MUX FRMR & M13/E13/G.747 MUX RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS3112+W | 功能描述:網(wǎng)絡控制器與處理器 IC TEMPE T3/E3 MUX FRMR & M13/E13/G.747 MUX RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS3112D1 | 功能描述:網(wǎng)絡控制器與處理器 IC TEMPE T3/E3 MUX FRMR & M13/E13/G.747 MUX RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS3112D1+ | 功能描述:網(wǎng)絡控制器與處理器 IC TEMPE T3/E3 MUX FRMR & M13/E13/G.747 MUX RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS3112DK | 功能描述:網(wǎng)絡開發(fā)工具 DS3112 Dev Kit RoHS:否 制造商:Rabbit Semiconductor 產(chǎn)品:Development Kits 類型:Ethernet to Wi-Fi Bridges 工具用于評估:RCM6600W 數(shù)據(jù)速率:20 Mbps, 40 Mbps 接口類型:802.11 b/g, Ethernet 工作電源電壓:3.3 V |
發(fā)布緊急采購，3分鐘左右您將得到回復。