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參數(shù)資料
| 型號(hào)： | CY28510 |
| 英文描述： | Clocks and Buffers |
| 中文描述： | 時(shí)鐘和緩沖器 |
| 文件頁數(shù)： | 9/13頁 |
| 文件大?。?/td> | 93K |
| 代理商： | CY28510 |
CY28510
Document #: 38-07542 Rev. **
Page 9 of 13
CLK_STOP# Clarification
The CLK_STOP# signal is an active low input used for
synchronous stopping and starting the CLK output clocks
while the rest of the clock generator continues to function.
CLK_STOP# Assertion
When CLK_STOP# pin is asserted low, all CLK outputs will be
stopped after being sampled by two rising CLK internal clock
edges.
CLK_STOP# Deassertion
The deassertion of the CLK_STOP# signal will cause all CLK
outputs that were stopped to resume normal operation in a
synchronous manner, synchronous manner meaning that no
short or stretched clock pulses will be produced when the
clock resumes. The maximum latency from the deassertion to
active outputs is no more than 2 CLK clock cycles
2.0V
VDD_ALL
CLK
REF
<1.2m sec
Figure 3. Power-up Signal Timing
CLK_STOP#
CLK
CLK Internal
Figure 4. CLK_STOP# Assertion Waveforms
CLK_STOP#
CLK
CLK Internal
Figure 5. CLK_STOP# Deassertion Waveforms
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| CY2901CDC | Microprocessor Slice |
| CY2901CDMB | Microprocessor Slice |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY28510OC | 制造商:Rochester Electronics LLC 功能描述:PERIPHERAL I/O CLOCK GENERATOR - Bulk |
| CY28510OCT | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Peripheral I/O Clock Generator |
| CY28512ZC-2 | 制造商:Cypress Semiconductor 功能描述: |
| CY28512ZC-2T | 制造商:Cypress Semiconductor 功能描述: |
| CY28514 WAF | 制造商:Cypress Semiconductor 功能描述: |
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