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| 型號： | CY28510 |
| 英文描述： | Clocks and Buffers |
| 中文描述： | 時鐘和緩沖器 |
| 文件頁數(shù)： | 8/13頁 |
| 文件大?。?/td> | 93K |
| 代理商： | CY28510 |
CY28510
Document #: 38-07542 Rev. **
Page 8 of 13
Calculating Load Capacitors
In addition to the standard external trim capacitors, trace
capacitance and pin capacitance must also be considered to
correctly calculate crystal loading. As mentioned previously,
the capacitance on each side of the crystal is in series with the
crystal. This means the total capacitance on each side of the
crystal must be 2 times the specified crystal load capacitance
(CL). While the capacitance on each side of the crystal is in
series with the crystal, trim capacitors (Ce1,Ce2) should be
calculated to provide equal capacitive loading on both sides.
As mentioned previously, the capacitance on each side of the
crystal is in series with the crystal. This means the total capac-
itance on each side of the crystal must be 2 times the specified
load capacitance (CL). While the capacitance on each side of
the crystal is in series with the crystal, trim capacitors
(Ce1,Ce2) should be calculated to provide equal capacitance
loading on both sides.
Use the following formulas to calculate the trim capacitor
values for Ce1 and Ce2.
CL
Ce
Cs
Ci
Crystal load capacitance
Actual loading seen by crystal using standard value trim capacitors
External trim capacitors
Stray capacitance (trace,etc)
Internal capacitance (lead frame, bond wires etc)
Layout and Decoupling Consideration
The V
DD
nets for each of the subgroups within each group are
not connected internally. What this implies is that each group
should have a separate V
DD
pool and it’s own 0.1
μ
F capacitor.
The more you can avoid external coupling across VDD planes,
the better each sub-net can operate at a different frequency,
whether jitter is on or off, or it is at a different frequency.
XTAL
Ce2
Ce1
Cs1
Cs2
X1
X2
Ci1
Ci2
Clock Chip
Trace
2.8pF
Trim
33pF
Pin
3 to 6p
Figure 2. Crystal Loading Example
Load Capacitance (each side)
Total Capacitance (as seen by the crystal)
Ce
= 2 * CL - (Cs + Ci)
Ce1 + Cs1 + Ci1
1
+
Ce2 + Cs2 + Ci2
1
(
)
1
=
CLe
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相關(guān)代理商/技術(shù)參數(shù) |
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| CY28510OC | 制造商:Rochester Electronics LLC 功能描述:PERIPHERAL I/O CLOCK GENERATOR - Bulk |
| CY28510OCT | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Peripheral I/O Clock Generator |
| CY28512ZC-2 | 制造商:Cypress Semiconductor 功能描述: |
| CY28512ZC-2T | 制造商:Cypress Semiconductor 功能描述: |
| CY28514 WAF | 制造商:Cypress Semiconductor 功能描述: |
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