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| 型號(hào)： | CY28510 |
| 英文描述： | Clocks and Buffers |
| 中文描述： | 時(shí)鐘和緩沖器 |
| 文件頁(yè)數(shù)： | 3/13頁(yè) |
| 文件大?。?/td> | 93K |
| 代理商： | CY28510 |
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CY28510
Document #: 38-07542 Rev. **
Page 3 of 13
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
clock output buffers, can be individually enabled or disabled.
The registers associated with the Serial Data Interface
initialize to their default setting upon power-up, therefore use
of this interface is optional. Clock device register changes are
normally made upon system initialization, yet the interface is
available at any time except power-down.
Data Protocol
The clock driver serial protocol accepts Byte Write, Byte Read,
Block Write, and Block Read operation from the controller. For
Block Write/Read operation, the bytes must be accessed in
sequential order from lowest to highest byte (most significant
bit first) with the ability to stop after any complete byte has
been transferred. For Byte Write and Byte Read operations,
the system controller can access individual indexed bytes. The
offset of the indexed byte is encoded in the command code,
as described in
Table 1
. The Block Write and Block Read
protocol is outlined in
Table 2
, while
Table 3
outlines the corre-
sponding byte write and byte read protocol.
The slave receiver address can be D0, D2, D4, or D6
depending on the state of the ADDSEL(0:1) pins.
26
VDDA
PWR
3.3V Power supply for analog PLLs.
25
VSSA
GND
Ground for analog PLLs.
4
VDDX
PWR
3.3V Power supply for oscillator.
5
VSSX
GND
Ground for oscillator.
8
VDDC
PWR
3.3V Power supply for core.
11
VSSC
GND
Ground for core.
Pin Description
(continued)
Pin
Name
Type
Power
Description
Table 1. Command Code Definition
Bit
Description
7
0 = Block read or block write operation
1 = Byte read or byte write operation
(6:0)
Byte offset for byte read or byte write operation. For block read or block write operations, these bits should
be ’0000000’
Table 2. Block Read and Block Write Protocol
Block Write Protocol
Block Read Protocol
Bit
Description
Bit
Description
1
Start
1
Start
2:8
Slave address – 7 bits
2:8
Slave address – 7 bits
9
Write = 0
9
Write = 0
10
Acknowledge from slave
10
Acknowledge from slave
11:18
Command Code – 8 bits
'00000000' stands for block operation
11:18
Command Code – 8 bits
'00000000' stands for block operation
19
Acknowledge from slave
19
Acknowledge from slave
20:27
Byte count from master – 8 bits
20
Repeat start
28
Acknowledge from slave
21:27
Slave address – 7 bits
29:36
Data byte 0 from master– 8 bits
28
Read = 1
37
Acknowledge from slave
29
Acknowledge from slave
38:45
Data byte 1 from master – 8 bits
30:37
Byte count from slave – 8 bits
46
Acknowledge from slave
38
Acknowledge
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY28510OC | 制造商:Rochester Electronics LLC 功能描述:PERIPHERAL I/O CLOCK GENERATOR - Bulk |
| CY28510OCT | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Peripheral I/O Clock Generator |
| CY28512ZC-2 | 制造商:Cypress Semiconductor 功能描述: |
| CY28512ZC-2T | 制造商:Cypress Semiconductor 功能描述: |
| CY28514 WAF | 制造商:Cypress Semiconductor 功能描述: |
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