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參數(shù)資料
| 型號： | CY28510 |
| 英文描述： | Clocks and Buffers |
| 中文描述： | 時鐘和緩沖器 |
| 文件頁數(shù)： | 5/13頁 |
| 文件大?。?/td> | 93K |
| 代理商： | CY28510 |
CY28510
Document #: 38-07542 Rev. **
Page 5 of 13
Notes:
1.
2.
The bandwidth of the non-spread PLL is 80 KHz.
Glitch free operation for both enabling and disabling Spread Spectrum
Byte 1: Clock Enable Register 2
Bit
7
6
5
4
3
2
1
0
@Pup
1
1
1
1
1
1
1
1
Name
CLKG1_0
CLKG1_1
CLKG1_2
CLKG1_3
CLKG2_0
CLKG2_1
CLKG3
REF
Description
1 = enabled, 0 = tri-state
1 = enabled, 0 = tri-state
1 = enabled, 0 = tri-state
1 = enabled, 0 = tri-state
1 = enabled, 0 = tri-state
1 = enabled, 0 = tri-state
1 = enabled, 0 = tri-state
1 = enabled, 0 = tri-state
Byte 2: Clock Spread Spectrum Control Register
Bit
7
6
5
@Pup
0
0
0
Name
Description
B2b7, B2b6: 00 = normal, 01 = testb_output, 10 = PD_resetb, 11 = normal
CPNTRL1
Charge Pump Control Bit1. See
Table 4
. Refer to CPNTRL0 in Byte 4, bit
0.
CLK output strength, 0 = low, 1 = high.
0=GFS(3:0) controls output frequency. 1 =I
2
C selection of output
frequency. Output frequencies should be set in Clock Frequency Select
Registers before enabling them.
Master Spread Spectrum Enable. 1 = enabled, 0 = disabled.
SST1 Select spread percentage. See
Table 5
SST0 Select spread percentage. See
Table 5
4
3
0
0
SWFSEL
2
1
0
1
0
0
MSTRSRD
SST1
SST0
Table 4. Charge Pump Control
[1]
SST1
0
0
1
1
SST0
0
1
0
1
% Spread
100%
114%
143%
88%
PLL Bandwidth
18 to 20 KHz
21 to 23 KHz
24 to 26 KHz
15 to 17 KHz
Table 5. Spread Spectrum Table
[2]
SST1
0
0
1
1
SST0
0
1
0
1
% Spread
–0.25% Down spread Lexmark profile
–0.50% Down spread Lexmark profile
–1.0% Down spread Lexmark profile
–1.0% Down spread Linear profile
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