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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉(h脿o)锛� | CS8420-CSZ |
| 寤犲晢锛� | Cirrus Logic Inc |
| 鏂囦欢闋�(y猫)鏁�(sh霉)锛� | 3/94闋�(y猫) |
| 鏂囦欢澶у皬锛� | 0K |
| 鎻忚堪锛� | IC SAMPLE RATE CONVERTER 28SOIC |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 27 |
| 椤炲瀷锛� | 閲囨ǎ鐜囪綁(zhu菐n)鎻涘櫒 |
| 鎳�(y墨ng)鐢細 | CD-R锛孌AT锛孌VD锛孧D锛孷TR |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 28-SOIC锛�0.295"锛�7.50mm 瀵級 |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 28-SOIC |
| 鍖呰锛� | 绠′欢 |
| 鐢�(ch菐n)鍝佺洰閷勯爜(y猫)闈細 | 759 (CN2011-ZH PDF) |
| 閰嶇敤锛� | 598-1782-ND - EVALUATION BOARD FOR CS8420 |
| 鍏跺畠鍚嶇ū锛� | 598-1125-5 |
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DS245F4
11
CS8420
SWITCHING CHARACTERISTICS - CONTROL PORT - IC MODE
Inputs: Logic 0 = 0 V, Logic 1 = VD+; CL = 20 pF.
16. Data must be held for sufficient time to bridge the 25 ns transition time of SCL.
Parameter
Symbol
Min
Typ
Max
Units
SCL Clock Frequency
fscl
-
100
kHz
Bus Free Time Between Transmissions
tbuf
4.7
-
渭s
Start Condition Hold Time (prior to first clock pulse)
thdst
4.0
-
渭s
Clock Low Time
tlow
4.7
-
渭s
Clock High Time
thigh
4.0
-
渭s
Setup Time for Repeated Start Condition
tsust
4.7
-
渭s
SDA Hold Time from SCL Falling
thdd
0-
-
渭s
SDA Setup Time to SCL Rising
tsud
250
-
ns
Rise Time of Both SDA and SCL Lines
tr
-
25
ns
Fall Time of Both SDA and SCL Lines
tf
-
25
ns
Setup Time for Stop Condition
tsusp
4.7
-
渭s
t buf
t
hdst
t
hdst
t
low
t r
t f
t
hdd
t
high
t sud
t sust
t susp
Stop
Start
Stop
Repeated
SDA
SCL
Figure 4. IC Mode Timing
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