Inputs: Logic 0 = DGND = AGND = 0 V, Logic 1 = VLC, C<" />
參數(shù)資料
型號: CS5346-CQZR
廠商: Cirrus Logic Inc
文件頁數(shù): 8/38頁
文件大?。?/td> 0K
描述: IC ADC AUD 103DB 200KHZ 48-LQFP
標準包裝: 2,000
位數(shù): 24
采樣率(每秒): 200k
數(shù)據(jù)接口: 串行
轉(zhuǎn)換器數(shù)目: 2
功率耗散(最大): 250mW
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 48-LQFP
供應(yīng)商設(shè)備封裝: 48-LQFP(7x7)
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 6 個單端,單極
配用: 598-1790-ND - BOARD EVAL FOR CS5346
16
DS861PP3
CS5346
SWITCHING CHARACTERISTICS - CONTROL PORT - IC FORMAT
Inputs: Logic 0 = DGND = AGND = 0 V, Logic 1 = VLC, CL =30pF.
13. Data must be held for sufficient time to bridge the transition time, tfc, of SCL.
Parameter
Symbol
Min
Max
Unit
SCL Clock Frequency
fscl
-
100
kHz
RST Rising Edge to Start
tirs
500
-
ns
Bus Free Time Between Transmissions
tbuf
4.7
-
s
Start Condition Hold Time (prior to first clock pulse)
thdst
4.0
-
s
Clock Low time
tlow
4.7
-
s
Clock High Time
thigh
4.0
-
s
Setup Time for Repeated Start Condition
tsust
4.7
-
s
SDA Hold Time from SCL Falling
thdd
0-
s
SDA Setup time to SCL Rising
tsud
250
-
ns
Rise Time of SCL and SDA
trc, trd
-1
s
Fall Time SCL and SDA
tfc, tfd
-
300
ns
Setup Time for Stop Condition
tsusp
4.7
-
s
Acknowledge Delay from SCL Falling
tack
300
1000
ns
t buf
t hdst
t
low
t
hdd
t high
t sud
Stop
Start
SDA
SC L
t irs
RS T
t hdst
t rc
t fc
t sust
t susp
Start
Stop
Repeated
t rd
t fd
t ack
Figure 5. Control Port Timing - IC Format
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