參數(shù)資料
型號(hào): CS5346-CQZR
廠商: Cirrus Logic Inc
文件頁(yè)數(shù): 21/38頁(yè)
文件大小: 0K
描述: IC ADC AUD 103DB 200KHZ 48-LQFP
標(biāo)準(zhǔn)包裝: 2,000
位數(shù): 24
采樣率(每秒): 200k
數(shù)據(jù)接口: 串行
轉(zhuǎn)換器數(shù)目: 2
功率耗散(最大): 250mW
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 48-LQFP
供應(yīng)商設(shè)備封裝: 48-LQFP(7x7)
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 6 個(gè)單端,單極
配用: 598-1790-ND - BOARD EVAL FOR CS5346
28
DS861PP3
CS5346
7. REGISTER DESCRIPTION
7.1
Chip ID - Register 01h
Function:
This register is Read-Only. Bits 7 through 4 are the part number ID, which is 1100b, and the remaining bits
(3 through 0) indicate the device revision as shown in Table 4 below.
7.2
Power Control - Address 02h
7.2.1
Freeze (Bit 7)
Function:
This function allows modifications to be made to certain control port bits without the changes taking effect
until the Freeze bit is disabled. To make multiple changes to these bits take effect simultaneously, set the
Freeze bit, make all changes, then clear the Freeze bit. The bits affected by the Freeze function are listed
7.2.2
Power-Down MIC (Bit 3)
Function:
The microphone preamplifier block will enter a low-power state whenever this bit is set.
7.2.3
Power-Down ADC (Bit 2)
Function:
The ADC pair will remain in a reset state whenever this bit is set.
7.2.4
Power-Down Device (Bit 0)
Function:
The device will enter a low-power state whenever this bit is set. The power-down bit is set by default and
must be cleared before normal operation can occur. The contents of the control registers are retained
when the device is in power-down.
76
543
21
0
PART3
PART2
PART1
PART0
REV3
REV2
REV1
REV0
REV[3:0]
Revision
0000
A1
Table 4. Device Revision
76
543
21
0
Freeze
Reserved
PDN_MIC
PDN_ADC
Reserved
PDN
Name
Register
Bit(s)
Mute
04h
2
Gain[5:0]
07h
5:0
Gain[5:0]
08h
5:0
Table 5. Freeze-able Bits
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