參數(shù)資料
型號: CS5346-CQZR
廠商: Cirrus Logic Inc
文件頁數(shù): 27/38頁
文件大?。?/td> 0K
描述: IC ADC AUD 103DB 200KHZ 48-LQFP
標(biāo)準(zhǔn)包裝: 2,000
位數(shù): 24
采樣率(每秒): 200k
數(shù)據(jù)接口: 串行
轉(zhuǎn)換器數(shù)目: 2
功率耗散(最大): 250mW
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 48-LQFP
供應(yīng)商設(shè)備封裝: 48-LQFP(7x7)
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 6 個單端,單極
配用: 598-1790-ND - BOARD EVAL FOR CS5346
DS861PP3
33
CS5346
7.10.1
Clock Error (Bit 3)
Function:
Indicates the occurrence of a clock error condition.
7.10.2
Overflow (Bit 1)
Function:
Indicates the occurrence of an ADC overflow condition.
7.10.3
Underflow (Bit 0)
Function:
Indicates the occurrence of an ADC underflow condition.
7.11 Status Mask - Address 0Eh
Function:
The bits of this register serve as a mask for the Status sources found in the register “Status - Address 0Dh”
on page 32. If a mask bit is set to 1, the error is unmasked, meaning that its occurrence will affect the status
register. If a mask bit is set to 0, the error is masked, meaning that its occurrence will not affect the status
register. The bit positions align with the corresponding bits in the Status register.
7.12 Status Mode MSB - Address 0Fh
7.13 Status Mode LSB - Address 10h
Function:
The two Status Mode registers form a 2-bit code for each Status register function. There are three ways to
update the Status register in accordance with the status condition. In the Rising-Edge Active Mode, the sta-
tus bit becomes active on the arrival of the condition. In the Falling-Edge Active Mode, the status bit be-
comes active on the removal of the condition. In Level-Active Mode, the status bit is active during the
condition.
00 - Rising edge active
01 - Falling edge active
10 - Level active
11 - Reserved
7
65
432
10
Reserved
ClkErrM
Reserved
OvflM
UndrflM
7
65
432
10
Reserved
ClkErr1
Reserved
Ovfl1
Undrfl1
Reserved
ClkErr0
Reserved
Ovfl0
Undrfl0
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