參數(shù)資料
型號(hào): CS5346-CQZR
廠商: Cirrus Logic Inc
文件頁(yè)數(shù): 26/38頁(yè)
文件大?。?/td> 0K
描述: IC ADC AUD 103DB 200KHZ 48-LQFP
標(biāo)準(zhǔn)包裝: 2,000
位數(shù): 24
采樣率(每秒): 200k
數(shù)據(jù)接口: 串行
轉(zhuǎn)換器數(shù)目: 2
功率耗散(最大): 250mW
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 48-LQFP
供應(yīng)商設(shè)備封裝: 48-LQFP(7x7)
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 6 個(gè)單端,單極
配用: 598-1790-ND - BOARD EVAL FOR CS5346
32
DS861PP3
CS5346
7.8.2
Analog Input Selection (Bits 2:0)
Function:
These bits are used to select the input source for the PGA and ADC. Please see Table 12.
7.9
Active Level Control - Address 0Ch
7.9.1
Active High/ Low (Bit 0)
Function:
When this bit is set, the INT pin functions as an active high CMOS driver.
When this bit is cleared, the INTpin functions as an active low open drain driver and will require an exter-
nal pull-up resistor for proper operation.
7.10 Status - Address 0Dh
For all bits in this register, a ‘1’ means theassociated condition has occurred at least once since the register
was last read. A ‘0’ means the associated condition has NOT occurred since the last reading of the register.
Status bits that are masked off in the associated mask register will always be ‘0’ in this register. This register
defaults to 00h.
PGASoft
PGAZeroCross
Mode
0
Changes to affect immediately
0
1
Zero Cross enabled
1
0
Soft Ramp enabled
1
Soft Ramp and Zero Cross enabled (default)
Table 11. PGA Soft Cross or Zero Cross Mode Selection
Sel2
Sel1
Sel0
PGA/ADC Input
0
Microphone-Level Inputs (+32 dB Gain Enabled)
0
1
Line-Level Input Pair 1
0
1
0
Line-Level Input Pair 2
0
1
Line-Level Input Pair 3
1
0
Line-Level Input Pair 4
1
0
1
Line-Level Input Pair 5
1
0
Line-Level Input Pair 6
1
Reserved
Table 12. Analog Input Multiplexer Selection
76
543
21
0
Reserved
Active_H/L
76
543
21
0
Reserved
ClkErr
Reserved
Ovfl
Undrfl
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