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參數(shù)資料
| 型號： | CS1311 |
| 文件頁數(shù)： | 8/25頁 |
| 文件大?。?/td> | 542K |
| 代理商： | CS1311 |
www.national.com
8
Revision 2.2
G
2.0
This section defines the signals and describes the external
interface of the CS1301/CS1311 media companion. Figure
2-1 shows the signals organized by their functional groups.
Signal Definitions
The remaining subsections of this chapter describe:
Section 2.1 "Ball Assignments": Provides a ball assign-
ment diagram and tables listing the signals sorted
according to ball number and alphabetically by signal
name.
Section 2.2 "Signal Descriptions": Detailed descriptions
of each signal according to functional group.
Section 2.3 "Reference Voltages": Discussion on ball
reference voltages.
2.1
The CS1301/CS1311 has a total of 169 functional pins,
excluding V
DDQ
, V
SSQ
, VREF_PCI, VREF_PERIPH, and
digital power/ground. For pins with 5.0V input capability,
the VREF_PCI or VREF_PERIPH determines 3.3V or 5.0V
input tolerance. Unused pins can remain floating/uncon-
nected; all pins that drive a clock should drive a series
resistor.
BALL ASSIGNMENTS
Table 2-1 shows the types of I/O circuits used by the
CS1301/CS1311 series. Note that the # symbol in a signal
name indicates that the active or asserted state occurs
when the signal is at a low voltage level. Otherwise, the
signal is asserted when at a high voltage level.
Figure 2-1. Functional Block Diagram
Table 2-1. Ball Type Descriptions
Modes
Description
I
Input only, except during boundary scan.
O
Output only, except during boundary scan.
OD
Open Drain output, active pull low, no active
drive high, requires external pull-up.
I/O
Input or Output.
I/OD
Input with Open Drain output, active pull low,
no active drive high, requires external pull-up.
MM_DQ[31:00]
MM_CKE[1:0]
MM_CLK[1:0]
MM_A[13:00]
MM_RAS#
MM_CAS#
MM_WE#
MM_DQM[3:0]
MM_CS[3:0]#
VREF_PCI
VREF_PERIPH
Video Out*
Interface
VO_CLK
VO_IO[2:1]
Memory
Interface
TRI_TIMER_CLK
TRI_RESET#
TRI_USERIRQ
System
Interface
Geode
CS1301/CS1311
TRI_CLKIN
JTAG_TCK
JTAG_TMS
JTAG_TDI
JTAG_TDO
JTAG
Interface
VO_DATA[07:00]
AO_OSCLK
AO_SCK
AO_SD[4:1]
AO_WS
SPDO
IIC-SDA
IIC-SCL
Audio Out
Interface
PCI_TRDY#
PCI_STOP#
PCI_IDSEL
PCI_DEVSEL#
PCI_REQ#
PCI_AD[31:00]
PCI_C/BE[3:0]#
PCI_SERR#
PCI_INTA#
PCI_INTB#
PCI_INTC#
PCI_CLK
PCI_GNT#
PCI_PERR#
PCI_FRAME#
PCI_IRDY#
PCI_INTD#
PCI Bus
Interface
PCI_PAR
VI_CLK
VI_DVALID
VI_DATA[09:00]
Video In
Interface
*Video In and Audio In are supported by third party software solutions, not by the National Semiconductor solution.
AI_OSCLK
AI_SCK
AI_SD
AI_WS
Audio In*
Interface
S/PDIF
Interface
ACCESS.bus
Interface
BOOT_CLK
TESTMODE
SCANCPU
Test and
Measurement
Interface
V
DDQ
V
SSQ
(Total of 24) V
DD
(Total of 40) V
CC
(Total of 55) V
SS
(Total of 8) NC
Power, Ground
and No
Connections
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