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參數(shù)資料
| 型號(hào)： | CS1311 |
| 文件頁數(shù)： | 15/25頁 |
| 文件大小： | 542K |
| 代理商： | CS1311 |
Revision 2.2
15
www.national.com
G
Signal Definitions
(Continued)
2.2.3
PCI Interface Signals
Signal Name
Ball
No.
Type
Description
PCI_CLK
T2
I
PCI Clock.
All PCI input signals are sampled with respect to the rising
edge of this clock. All PCI outputs are generated based on this clock.
This clock is required for normal operation of the PCI module.
PCI_AD[31:00]
See Table
2-3 on
page 12
I/O
Multiplexed Address and Data.
PCI_C/BE0#
M3
I/O
Multiplexed Bus Commands and Byte-Enables
. High for command,
low for byte-enable.
PCI_C/BE1#
J3
PCI_C/BE2#
D2
PCI_C/BE3#
B3
PCI_PAR
H1
I/O
Parity.
Even parity across AD and C/BE# lines.
PCI_FRAME#
E2
I/O
Frame Sustained TRI-STATE.
Frame is driven by a master to indicate
the beginning and duration of an access.
PCI_IRDY#
E1
I/O
Initiator Ready Sustained TRI-STATE.
Initiator Ready indicates that
the bus master is ready to complete the current data phase.
PCI_TRDY#
F3
I/O
Target Ready Sustained TRI-STATE.
Target Ready indicates that the
bus target is ready to complete the current data phase.
PCI_STOP#
G2
I/O
Stop Sustained TRI-STATE.
Indicates that the target is requesting that
the master stop the current transaction.
PCI_IDSEL
A2
I
ID Select.
Used as chip select during configuration read/write cycles.
PCI_DEVSEL#
F1
I/O
Device Select Sustained TRI-STATE.
Indicates whether any device on
the bus has been selected.
PCI_REQ#
B7
O
Request.
Driven by the CS1301/CS1311 as a PCI bus master to request
use of the PCI bus.
PCI_GNT#
B5
I
Grant.
Indicates to the CS1301/CS1311 that access to the PCI bus has
been granted.
PCI_PERR#
G1
I/O
Parity Error Sustained TRI-STATE.
Parity error generated/received by
CS1301/CS1311.
PCI_SERR#
H2
OD
System Error.
This signal is asserted when operating as a target and
detecting an address parity error.
PCI_INTA#
C9
I/OD
PCI Interrupts A, B, C, and D.
Can operate as an input (power-up
default) or output, as determined by direction control bits in PCI MMIO
register INT_CTL.
As an input, PCI_INT# can be used to receive PCI interrupt requests
(normal PCI use is active low, level-sensitive mode, but the VIC can be
set to treat these as a positive edge triggered mode). As an input,
PCI_INT# can also be used as a general interrupt request if not needed
for PCI.
As an output, the value of a PCI_INT# can be programmed through PCI
MMIO registers to generate interrupts for other PCI masters.
PCI_INTB#
A8
I/O/OD
PCI_INTC#
B8
I/OD
PCI_INTD#
A7
I/OD
Note:
Current buffer design allows drive/receive from either 3.3V or 5.0V PCI bus.
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