參數(shù)資料
型號(hào)： CS1311
文件頁(yè)數(shù)： 13/25頁(yè)
文件大小： 542K
代理商： CS1311
Revision 2.2
13
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Signal Definitions
(Continued)
2.2
SIGNAL DESCRIPTIONS
2.2.1
System Interface Signals
Signal Name
Ball
No.
Type
Description
TRI_CLKIN
L20
I
Main Input Clock.
The SDRAM clock outputs (MM_CLK0 and
MM_CLK1) can be set to 2x or 3x this frequency. The on-chip DSPCPU
clock (DSPCPU_CLK) can be set to 1x, 5/4, 4/3, 3/2 or 2x the SDRAM
clock frequency. The maximum recommended ppm level is ±100 ppm or
lower to improve jitter on generated clocks. The duty cycle should not
exceed 30/70% asymmetry.
The operating limits of the internal PLLs are:
27 MHz < Output of the SDRAM PLL < 200 MHz
33 MHz < Output of the CPU PLL < 266 MHz
These are not the speed grades of the chips, just the PLL limits.
TRI_USERIRQ
G20
I
General Purpose Level/Edge Interrupt Input.
Vectored interrupt
source number 4.
TRI_TIMER_CLK
H19
I
External General Purpose Clock Source for Timers
. Maximum 40
MHz.
TRI_RESET#
G19
I
CS1301/CS1311 RESET Input.
This pin can be tied to the PCI_RST#
signal in the PCI bus systems. Upon releasing RESET, CS1301/CS1311
initiates its boot protocol.
VREF_PCI
F2
PWR
PCI Voltage Reference.
Determines the mode of operation of the PCI
pins. VREF_PCI must be connected to V
SS
(0V) for use in 3.3V PCI sig-
naling environment, as is the case for a Geode SCx200 system.
The supply to this pin should be AC bypassed and provide 40 mA of DC
sink or source capability.
VREF_PERIPH
C18
PWR
Peripheral Voltage Reference.
Determines the mode of operation of
the I/O pins listed in Section 2.3 "Reference Voltages" on page 22.
VREF_PERIPH must be connected to 5.0V if the designated I/O pins
listed in Section 2.3 should be 5.0V input voltage capable.
VREF_PERIPH must be connected to V
SS
(0V) if the designated I/O
pins listed in Section 2.3 are 3.3V only inputs.
The supply to this pin should be AC bypassed and provide 40 mA of DC
sink or source capability.
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