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參數(shù)資料
| 型號： | CS1311 |
| 文件頁數(shù)： | 17/25頁 |
| 文件大?。?/td> | 542K |
| 代理商： | CS1311 |
Revision 2.2
17
www.national.com
G
Signal Definitions
(Continued)
2.2.5
Video Out Interface Signals
Signal Name
Ball
No.
Type
Description
VO_CLK
J19
I/O
Clock.
The VO module emits VO_DATA[07:00] on a positive edge of
VO_CLK. VO_CLK can be configured as an input (reset default) or out-
put.
If configured as an input: VO_CLK is received from external display
clock master circuitry.
If configured as an output: The CS1301/CS1311 emits a programmable
clock frequency. The emitted frequency can be set between approxi-
mately 4 and 81 MHz with a sub-Hertz resolution. The clock generated is
frequency accurate and has low jitter properties due to a combination of
an on-chip DDS (Direct Digital Synthesizer) and VCO/PLL.
If used as an output, a board level 27 to 33
series resistor is recom-
mended to reduce ringing.
VO_IO1
J18
I/O
Input/Output 1.
This pin can function as HS (Horizontal Sync) output or
as STMSG (Start Message) output.
If set as HS output: VO_IO1 outputs the HS output signal.
In message passing mode, VO_IO1 acts as the STMSG output signal.
VO_IO2
H20
I/O
Input/Output 2.
This pin can function as FS (Frame Sync) input, FS out-
put or as ENDMSG (End Message) output.
If set as FS input, it can be set to respond to positive or negative edge
transitions.
If the VO module operates in external sync mode and the selected tran-
sition occurs, the VO module sends two fields of video data. Note: this
works only once after a reset.
In message passing mode, this pin acts as ENDMSG output signal.
VO_DATA[07:00]
K20, K12,
M20,
M19,
M18,N20,
N19, P20
O
Data Bus.
CCIR-656 style YUV 4:2:2 digital output data, or general pur-
pose high-speed data output channel. Output changes on positive edge
of VO_CLK.
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