參數(shù)資料
型號: CS1311
文件頁數(shù): 16/25頁
文件大小: 542K
代理商: CS1311
www.national.com
16
Revision 2.2
G
Signal Definitions
(Continued)
2.2.4
Video In Interface Signals
Signal Name
Ball
No
Type
Description
VI_CLK
C20
I/O
Clock.
This signal can be configured as either an input or an output:
If configured as an input (power-up default): A positive transition on this
incoming video clock pin samples VI_DATA[09:00] if VI_DVALID is high.
If VI_DVALID is low, VI_DATA[09:00] is ignored. Clock and data rates of
up to 81 MHz are supported. The CS1301/CS1311 supports an addi-
tional mode where VI_DATA[09:08] in message passing mode are not
affected by the VI_DVALID signal.
If configured as an output: VI_CLK performs as a programmable output
clock to drive an external video A/D converter. It can be programmed to
emit integral dividers of DSPCPU_CLK.
If used as an output, a board level 27 to 33
series resistor is recom-
mended to reduce ringing.
VI_DVALID
A17
I
Data Valid.
VI_DVALID indicates that valid data is present on
VI_DATA[09:00]. If high, VI_DATA will be accepted on the next VI_CLK
positive edge. If low, VI_DATA[09:00] will not be sampled. However, the
CS1301/CS1311 supports an additional mode where VI_DATA[9:8] in
message passing mode are not affected by the VI_DVALID signal.
VI_DATA[07:00]
B18,C17,
A19, A20,
B19, B20,
C19, D18
I
Data Bus Lines [7:0].
CCIR-656 style YUV 4:2:2 data from a digital
camera or general purpose high speed data input pins. Sampled on
VI_CLK if VI_DVALID is high.
VI_DATA[09:08]
B17, A18
Data Bus Lines [9:8].
Extension high speed data input bits to allow use
of 10-bit video A/D converters in raw10 modes. VI_DATA[08] serves as
START and VI_DATA[09] as END message input in message passing
mode. Sampled on positive transitions of VI_CLK if VI_DVALID is high.
The CS1301/CS1311 supports an additional mode where
VI_DATA[09:08] in message passing mode are not affected by the
VI_DVALID signal.
Note:
Video In and Audio In are supported by third party software solutions, not by the National solution.
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