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| 型號(hào)： | COP942CT |
| 文件頁數(shù)： | 23/36頁 |
| 文件大?。?/td> | 479K |
| 代理商： | COP942CT |
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Control Registers
(Continued)
HC
Bit 7
The Half-Carry bit is also effected by all the instructions that
effect the Carry flag. The flag values depend upon the in-
struction. For example, after executing the ADC instruction
the values of the Carry and the Half-Carry flag depend upon
the operands involved. However, instructions like SET C and
RESET C will set and clear both the carry flags. Table 9 lists
the instructions that effect the HC and the C flags.
C
TPND
ENTI
IPND BUSY
ENI
GIE
Bit 0
TABLE 9. Instructions Effecting HC and C Flags
Instr.
ADC
HC Flag
C Flag
Depends on
operands
Depends on
operands
Set
Set
Depends on
operands
Depends on
operands
Set
Set
SUBC
SET C
RESET
C
RRC
Depends on
operands
Depends on
operands
CNTRL2 REGISTER (ADDRESS 00CC)
MC3 MC2 MC1CMPEN CMPRD CMPOEWDUDF unused
R/W R/W R/W
R/W
R/O
Bit 7
MC3
Modulator/Timer Control Bit
MC2
Modulator/Timer Control Bit
MC1
Modulator/Timer Control Bit
CMPEN Comparator Enable Bit
CMPRD Comparator Read Bit
CMPOE Comparator Output Enable Bit
WDUDF WATCHDOG Timer Underflow Bit (Read Only)
R/W
R/O
Bit 0
WDREN REGISTER (ADDRESS 00CD)
WDRENWATCHDOG Reset Enable Bit (Write Once Only)
UNUSED
Bit 7
WDREN
Bit 0
Memory Map
All RAM, ports and registers (except A and PC) are mapped
into data memory address space.
TABLE 10. Memory Map
ADDRESS
00–6F
70–7F
CONTENTS
On-Chip RAM bytes (112 bytes)
Unused RAM address
(Reads as all ones)
Unused RAM address
(Reads Undefined Data)
Reserved
MIWU Edge Select Register
(Reg:WKEDG)
80–BF
C0–C7
C8
ADDRESS
C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
D4
D5
D6
D7
D8–DB
DC
DD–DF
E0–EF
E0–E7
E8
E9
EA
EB
EC
ED
EE
EF
F0–FF
FC
FD
FE
Reading other unused memory locations will return unde-
fined data.
CONTENTS
MIWU Enable Register (Reg:WKEN)
MIWU Pending Register (Reg:WKPND)
Reserved
Control2 Register (CNTRL2)
WATCHDOG Register (WDREG)
WATCHDOG Counter (WDCNT)
Modulator Reload (MODRL)
Port L Data Register
Port L Configuration Register
Port L input Pins (read only)
Reserved for Port L
Port G Data Register
Port G Configuration Register
Port G Input pins (read only)
Port I Input pins (read only)
Reserved for Port C
Port D Data Register
Reserved for Port D
On-Chip Functions and Registers
Reserved for Future Parts
Reserved
MICROWIRE Shift Register
Timer Lower Byte
Timer Upper Byte
Timer1 Autoreload Register Lower Byte
Timer1 Autoreload Register Upper Byte
CNTRL1 Control Register
PSW Register
On-Chip RAM mapped as Registers
X Register
SP Register
B Register
Addressing Modes
There are ten addressing modes, six for operand addressing
and four for transfer of control.
OPERAND ADDRESSING MODES
REGISTER INDIRECT
This is the “normal” addressing mode for the chip. The oper-
and is the data memory addressed by the B or X pointer.
REGISTER INDIRECT WITH AUTO POST
INCREMENT OR DECREMENT
This addressing mode is used with the LD and X instruc-
tions. The operand is the data memory addressed by the
B
or
X
pointer. This is a register indirect mode that automati-
cally post increments or post decrements the
B
or
X
pointer
after executing the instruction.
C
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