參數(shù)資料
型號(hào)： COP942CT
文件頁(yè)數(shù)： 12/36頁(yè)
文件大?。?/td> 479K
代理商： COP942CT
Functional Description
(Continued)
decremented and tested. Three specific registers: X, B, and
SP are mapped into this space, the other registers are avail-
able for general usage.
The instruction set permits any bit in memory to be directly
set, reset or tested. All I/O and registers (except A and PC)
are memory mapped; therefore, I/O bits and register bits can
be directly and individually set, reset and tested; except the
write once only bit (WDREN, WATCHDOG Reset Enable),
and the unused and read only bits in the CNTRL2 and
WDREG registers.
Note:
RAM contents are undefined upon power-up.
Reset
EXTERNAL RESET
The RESET input pin when pulled low initializes the micro-
controller. The user must insure that the RESET pin is held
low until V
CC
is within the specified voltage range and the
clock is stabilized.An R/C circuit with a delay 5x greater than
the power supply rise time is recommended (Figure 3). The
device immediately goes into reset state when the RESET
input goes low. When the RESET pin goes high the device
comes out of reset state synchronously. The device will be
running within two instruction cycles of the RESET pin going
high. The following actions occur upon reset:
Register
Initialization
Port L
Port G
Port D
PC
RAM Contents
TRI-STATE
TRI-STATE
HIGH
CLEARED
RANDOM with Power On
Reset
UNAFFECTED with external
Reset (power already applied)
Same as RAM
CLEARED
B, X, SP
PSW, CNTRL1, CNTRL2
and WDREG Reg.
Multi-Input Wake-up
Reg.
(WKEDG, WKEN)
(WKPND)
Data and Configuration
Registers for L and G
WATCHDOG Timer
CLEARED
UNKNOWN
CLEARED
Prescaler/Counter each
loaded with FF
The device comes out of the HALT mode when the RESET
pin is pulled low. In this case, the user has to ensure that the
RESET signal is low long enough to allow the oscillator to re-
start.An internal 256 t
C
delay is normally used in conjunction
with the two pin crystal oscillator. When the device comes
out of the HALT mode through Multi-Input Wake-up, this de-
lay allows the oscillator to stabilize.
The following additional actions occur after the device
comes out of the HALT mode via the RESET pin.
If a two pin crystal/resonator oscillator is being used:
RAM Contents:
Timer T1 and A Contents:
WATCHDOG Timer
Prescaler/Counter:
If the external or RC clock option is being used:
UNAFFECTED
UNKNOWN
CHANGED
RAM Contents:
Timer T1 and A Contents:
WATCHDOG Timer
Prescaler/Counter:
The external RESET takes priority over the Brown Out Re-
set.
Note:
If the RESET pin is pulled low while Brown Out occurs (Brown Out cir-
cuit has detected Brown Out condition), the external reset will not oc-
cur until the Brown Out condition is removed. External reset has prior-
ity only if V
CC
is greater than the Brown Out Voltage.
UNCHANGED
UNCHANGED
CHANGED
WATCHDOG RESET
With WATCHDOG enabled, the WATCHDOG logic resets
the device if the user program does not service the WATCH-
DOG timer within the selected service window. The WATCH-
DOG reset does not disable the WATCHDOG. Upon
WATCHDOG reset, the WATCHDOG Prescaler/Counter are
each initialized with FF Hex.
The following actions occur upon WATCHDOG reset that are
different from external reset.
WDREN
WATCHDOG Reset Enable bit UNCHANGED
WDUDF
WATCHDOG Underflow bit UNCHANGED
Additional initialization actions that occur as a result of
WATCHDOG reset are as follows:
Port L:
Port G:
Port D:
PC:
RAM Contents:
B, X, SP:
PSW, CNTRL1 and CNTRL2
(except WDUDF Bit) Registers:
Multi-Input Wake-up Registers
(WKEDG,WKEN):
(WKPND):
Data and Configuration
Registers for L and G:
WATCHDOG Timer:
TRI-STATE
TRI-STATE
HIGH
CLEARED
RANDOM
UNAFFECTED
CLEARED
CLEARED
UNKNOWN
CLEARED
Prescaler/Counter
each loaded with FF
DS012851-14
RC
>
5 x Power Supply Rise Time
FIGURE 3. Recommended Reset Circuit
C
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