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| 型號： | COP942CT |
| 文件頁數(shù)： | 22/36頁 |
| 文件大?。?/td> | 479K |
| 代理商： | COP942CT |
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Multi-Input Wake-Up
(Continued)
large amplitude to meet the Schmitt trigger specs. This
Schmitt trigger is not part of the oscillator closed loop. The
start-up time-out from the WATCHDOG timer enables the
clock signals to be routed to the rest of the chip.
Interrupts
The device has a sophisticated interrupt structure to allow
easy interface to the real world. There are three possible in-
terrupt sources, as shown below.
A maskable interrupt on external GO input (positive or nega-
tive edge sensitive under software control)
A maskable interrupt on timer carry or timer capture
A non-maskable software/error interrupt on opcode zero
INTERRUPT CONTROL
The GIE (global interrupt enable) bit enables the interrupt
function. This is used in conjunction with ENI and ENTI to se-
lect one or both of the interrupt sources. This bit is reset
when interrupt is acknowledged.
ENI and ENTI bits select external and timer interrupts re-
spectively. Thus be user can select either or both source to
interrupt the microcontroller when GIE is enabled.
IEDG selects the external interrupt edge (0— rising edge,
1 =falling edge). The user can get an interrupt on both rising
and falling edges by toggling the state of IEDG bit after each
interrupt.
IPND and TPND bits signal which interrupt is pending. After
an interrupt is acknowledged, the user can check these two
bits to determine which interrupt is pending. This permits the
interrupts to be prioritized under software. The pending flags
have to be cleared by the user. Setting the GIE bit high in-
side the interrupt subroutine allows nested interrupts. The
software interrupt does not reset the GIE bit. This means that
the controller can be interrupted by other interrupt sources
while servicing the software interrupt.
INTERRUPT PROCESSING
The interrupt, once acknowledged, pushes the program
countermen counter (PC) onto the stack and the stack
pointer (SP) is decremental twice. The Global Interrupt En-
able (GIE) bit is reset to disable further interrupts. The micro-
controller then vectors to the address 00FFH and resumes
execution from that address. This process takes 7 cycles to
complete. At end of the interrupt subroutine, any of the fol-
lowing three instructions return the processor back to the
main program: RET, RETSK or RETI. Either one of the three
instructions will pop the stack into the program counter (PC).
The stack pointer is then incremented twice. The RETI in-
struction additionally sets the GIE bit to re-enable further in-
terrupts.
Any of the three instructions can be used to return from a
hardware interrupt subroutine. The RETSK instruction
should be used when returning from a software interrupt
subroutine to avoid entering an infinite loop.
Note:
There is always the possibility of an interrupt occurring during an in-
struction which is attempting to reset the GIE bit or any other interrupt
enable bit. If this occurs when a single cycle instruction is being used
to reset the interrupt enable bit, the interrupt enable bit will be reset but
an interrupt may still occur. This is because interrupt processing is
started at the same time as the interrupt bit is being reset. To avoid this
scenario, the user should always use a two, three, or four cycle instruc-
tion to reset interrupt enable bits.
DETECTION OF ILLEGAL CONDITIONS
The device incorporates a hardware mechanism that allows
it to detect illegal conditions which may occur from coding er-
rors, noise and “brown out” voltage drop situations. Specifi-
cally, it detects cases of executing out of undefined ROM
area and unbalanced stack situations.
Reading an undefined ROM location returns 00 (hexadeci-
mal) as its contents. The opcode for a software interrupt is
also “00”. Thus a program accessing undefined ROM will
cause a software interrupt. Reading undefined RAM location
returns an FF (hexadecimal). The subroutine stack on the
device grows down for each subroutine call. By initializing
the stack pointer to the top of RAM, the first unbalanced re-
turn instruction will cause the stack pointer to address unde-
fined RAM. As a result the program will attempt to execute
from FFFF (hexadecimal), which is an undefined ROM loca-
tion and will trigger a software interrupt.
Control Registers
CNTRL1 REGISTER (ADDRESS 00EE)
The Timer and MICROWIRE control register contains the fol-
lowing bits:
SL1 and SL0 Select the MICROWIRE clock divide-by
(00 = 2, 01 = 4, 1x = 8)
IEDG
External interrupt edge polarity select
MSEL
Selects G5 and G4 as MICROWIRE signals
SK and SO respectively
TRUN
Used to start and stop the timer/counter
(1 = run, 0 = stop)
TC1
Timer T1 Mode Control Bit
TC2
Timer T1 Mode Control Bit
TC3
Timer T1 Mode Control Bit
TC1
Bit 7
TC2
TC3
TRUN
MSEL
IEDG
SL1
SL0
Bit 0
PSW REGISTER (ADDRESS 00EF)
The PSW register contains the following select bits:
GIE
Global interrupt enable (enables interrupts)
ENI
External interrupt enable
BUSY MICROWIRE busy shifting flag
PND
External interrupt pending
ENTI
Timer T1 interrupt enable
TPND Timer T1 interrupt pending (timer Underflow or cap-
ture edge)
C
Carry Flip/flop
HC
Half carry Flip/flop
DS012851-28
FIGURE 15. Interrupt Block Diagram
C
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