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| 型號： | COP942CT |
| 文件頁數(shù)： | 19/36頁 |
| 文件大小： | 479K |
| 代理商： | COP942CT |
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Modulator/Timer
(Continued)
2.
Variable Duty Cycle:
When MC3=0 and MC2=1, a variable duty cycle PWM
signal is generated on the L7 output pin. The counter is
clocked by t
. In this mode the 16-bit timer T1 along with
the 8-bit down counter are used to generate a variable
duty cycle PWM signal. The timer T1 underflow sets
MC1 which starts the down counter and it also sets L7
high (L7 should be configured as an output). When the
counter underflows the MC1 control bit is reset and the
L7 output will go low until the next timer T1 underflow.
Therefore, the width of the output pulse is controlled by
the 8-bit counter and the pulse duration is controlled by
the 16-bit timer T1 (Figure 13) Timer T1 must be config-
ured in “PWM Mode/Toggle TIO Out” (CNTRL1 Bits
7,6,5 = 101).
Table 7 shows the different operation modes for the
Modulator/Timer.
TABLE 7. Modulator/Timer Modes
Control bits in
CNTRL2(00CC)
MC2
0
0
OPERATION MODE
L7 Function
MC3
0
0
MC1
0
1
Normal I/O
50% duty cycle mode
(clocked by t
C
)
Variable duty cycle
mode (clocked by t
C
)
using Timer 1
underflow
Modulator mode
(clocked by t
C
)
Modulator mode
(clocked by CKI)
0
1
X
1
0
X
1
1
X
Note 17:
MC1, MC2 and MC3 control bits are cleared upon reset.
INTERNAL DATA BUS
DS012851-22
FIGURE 11. Mode 1: Modulator Block Diagram/Output Waveform
C
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