- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄379891 > CL-PS7110-VI-A (CIRRUS LOGIC INC) Low-Power System-on-a-Chip PDF資料下載
參數(shù)資料
| 型號(hào)： | CL-PS7110-VI-A |
| 廠商： | CIRRUS LOGIC INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Low-Power System-on-a-Chip |
| 中文描述： | MROM, RISC MICROCONTROLLER, PQFP208 |
| 封裝： | VQFP-208 |
| 文件頁(yè)數(shù)： | 45/82頁(yè) |
| 文件大小： | 1101K |
| 代理商： | CL-PS7110-VI-A |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)當(dāng)前第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)
May 1997
45
DATA BOOK v1.5
PROGRAMMING INTERFACE
CL-PS7110
Low-Power System-on-a-Chip
ADCKSEL
Microwire
/SPI
peripheral clock speed select. This 2-bit field selects the frequency
of the ADC sample clock, which is twice the frequency of the synchronous serial ADC
interface clock.
Table 3-5
shows the available frequencies.
WAKEDIS
If this bit is set, switch-on (through the wake-up input) is disabled.
IRTXM
IrDA Tx mode bit. This bit controls the IrDA encoding strategy. Clearing this bit means
each ‘0’ bit transmitted is represented as a pulse of width 3/16th of the bit rate period.
Setting this bit means each ‘0’ bit is represented as a pulse of width 3/16th of the
period of 115,000 bit rate clock, that is, 1.6
μ
s, regardless of the selected bit rate. Set-
ting this bit reduces power consumption, but probably reduces transmission dis-
tances.
Bits 21–23
Reserved. Write has no effect, always reads ‘0’.
3.2.12 SYSFLG — System Status Flags Register
The System Status Flags register is a 32-bit read-only register that indicates various system information.
The bits in this register are defined in
Table 3-6
.
Table 3-5.
ADCCLK Frequencies
ADCKSEL
ADC Sample frequency (kHz) —
SMPCLK
ADC interface frequency (kHz) —
ADCCLK
00
8
4
01
32
16
10
128
64
11
256
128
Table 3-6.
Bits in the System Status Flags Register
7
4
3
2
1
0
DID
WUON
WUDR
DCDET
MCDR
15
14
13
12
11
10
9
8
CLDFLG
PFFLG
RSTFLG
NBFLG
UBUSY
DCD
DSR
CTS
23
22
21
16
UTXFF
URXFE
RTCDIV
31
30
29
28
27
26
25
24
VERID
Reserved
Reserved
BOOT8BIT
SSIBUSY
CTXFF
CRXFE
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CL-PS7110 | Low-Power System-on-a-Chip |
| CL-PS7111 | Low-Power System-on-a-Chip |
| CL-PS7111-VC-A | Low-Power System-on-a-Chip |
| CL-PS7500FE | System-on-a Chip for Internet Appliance |
| CL-SH8665 | Integrated ATA Drive microcontroller(集成ATA驅(qū)動(dòng)微控制器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CL-PS7111 | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:Low-Power System-on-a-Chip |
| CL-PS7111(208LQFP) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Logic IC |
| CL-PS7111(256PBGA) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Logic IC |
| CL-PS7111-VC-A | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:Low-Power System-on-a-Chip |
| CL-PS7500FE | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:System-on-a Chip for Internet Appliance |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。