參數(shù)資料
型號(hào)： CL-PS7110-VI-A
廠商： CIRRUS LOGIC INC
元件分類(lèi)： 微控制器/微處理器
英文描述： Low-Power System-on-a-Chip
中文描述： MROM, RISC MICROCONTROLLER, PQFP208
封裝： VQFP-208
文件頁(yè)數(shù)： 13/82頁(yè)
文件大?。?/td> 1101K
代理商： CL-PS7110-VI-A
May 1997
13
DATA BOOK v1.5
FUNCTIONAL DESCRIPTION
CL-PS7110
Low-Power System-on-a-Chip
1.2.1
Clocking
The main bus clock runs at 18.432 MHz and is derived from the output of the 3.6864-MHz oscillator, using
an on-chip PLL to multiply by 10 and then divide by 2 to ensure a proper 50–50 mark space ratio is
achieved. The main bus clock is routed only to the ARM710A, the LCD controller, the memory controller
peripherals, and the baud-rate generator. Clocks required for the other peripherals are lower frequency,
and are generally not required to be synchronous to the main bus clock. These clocks are centrally gen-
erated using ripple count stages where possible to minimize power consumption, and distributed to the
appropriate peripherals.
1.2.2
CPU Core
The ARM710A microprocessor is a 32-bit RISC processor directly connected to the 8-Kbyte unified
cache. This cache has 512 lines of four words arranged as a four-way set-associative cache. The cache
is directly connected to the ARM710A microprocessor and caches the virtual addressfrom the processor.
The MMU translates the virtual address into a physical address, it contains a 64-entry TLB (translation
look aside buffer) and is post cache that is, it only translates external memory references (cache misses)
to save power.
Refer to descriptions of the Interrupt Status register (INTSR) and Internal Mask register (INTMR) in the
ARM710A Data Sheet.
1.2.3
Interrupt Controller
The ARM710A has two interrupt types: IRQ (interrupt request) and FIQ (fast interrupt request). The inter-
rupt controller in the CL-PS7110 controls interrupts from 16 different sources. Twelve interrupt sources
are mapped to the IRQ input and four sources are mapped to the FIQ input. FIQs have a higher priority
than IRQs; if two interrupts within the same group (IRQ or FIQ) are active, software must resolve the order
in which they are serviced.
All interrupts are level-sensitive hat is, they must conform to the following sequence.
1)
The device asserts the appropriate interrupt request line.
2)
If the appropriate bit is set in the Interrupt Mask register, either FIQ or IRQ is asserted by the interrupt con-
troller.
3)
If interrupts are enabled, the processor jumps to the appropriate vector.
4)
Interrupt dispatch software reads the Interrupt Status register to establish the source(s) of the interrupt, then
calls the appropriate interrupt service routine(s).
5)
Software in the interrupt service routine clears the interrupt source by some action specific to the device
requesting the interrupt (for example, reading the UART Rx register).
6)
The interrupt service routine can then re-enable interrupts, any other pending interrupts are serviced in a sim-
ilar way or returned to the interrupt dispatch code, which checks for any more pending interrupts and dis-
patches them accordingly.
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