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| 型號： | CL-PS7110-VI-A |
| 廠商： | CIRRUS LOGIC INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Low-Power System-on-a-Chip |
| 中文描述： | MROM, RISC MICROCONTROLLER, PQFP208 |
| 封裝： | VQFP-208 |
| 文件頁數(shù)： | 27/82頁 |
| 文件大?。?/td> | 1101K |
| 代理商： | CL-PS7110-VI-A |
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May 1997
27
DATA BOOK v1.5
FUNCTIONAL DESCRIPTION
CL-PS7110
Low-Power System-on-a-Chip
1.2.18 Battery Management
There are four pins for battery management:
BATOK
This signal is derived from a comparator that is set to switch when the main battery reaches its end-of-life
point. A transition to low will generate an FIQ interrupt. The operating system has to ensure the system
is powered down to Standby mode to not drain the battery. Hardware inside the CL-PS7110 prevents the
system from starting up unless a power-fail condition (NPWRFL deactive) is removed.
NEXTPWR
This input should be driven when an external power supply other than the main battery is powering the
system. Only when this input is high with (NPWRFL deactive) the system may exit the standby state. This
prevents the system from attempting to wake up.
BATCHG
When asserted this input will not generate an interrupt. It simply signals that there is no battery present.
It may be generated by an external comparator that senses the battery voltage.
NPWRFL
This input will immediately put the system in standby state. The system is, however, assured that the
DRAM access is completed and put into Self-refresh mode
.
1.2.19 State Control
The CL-PS7110 supports three basic power states: standby, idle, and operating.The standby state is the
equivalent of the computer being switched ‘off’, that is, no display and the main oscillator shut down. The
idle state is when the device is functioning, all oscillators are running, but the processor clock is halted
while it waits for an event such as a key press. The operating state is the same as the idle state, except
that the processor clock is running.
In the standby state, all system memory and states are maintained, and the system time is kept up to date.
The main oscillator is disabled and the system is static, except for the low-power (32-kHz) watch crystal
oscillator and divider chain to the realtime clock. The ‘run’ signal is driven low when in the standby state.
When first powered up or reset by the NPOR (Not Power On Reset) signal, the state is forced into the
standby state. This is known as a ‘cold’ reset and is the only completely asynchronous reset to the
CL-PS7110. The transition to the operating state is caused by a rising edge on the wake-up input signal
(the user presses any wake-up keys), or by asserting a selected interrupt. Once self-refresh is enabled
for the DRAMs, any transition to the standby state forces the DRAMs to the self-refresh state before stop-
ping the oscillator.
Once in the operating state, the idle state s entered by writing to a special internal register location in the
CL-PS7110. If an interrupt becomes active in the idle state, execution of the next instruction continues.
The system can also be forced into the standby state by hardware if the NPWRFL or NURESET inputs
are forced low. In this case, the transition is synchronized with DRAM cycles to avoid any glitches or short
cycles.
A write to another internal register location causes the transition from the operating state to the standby
state.
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