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參數資料
| 型號： | CL-PS7110-VI-A |
| 廠商： | CIRRUS LOGIC INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Low-Power System-on-a-Chip |
| 中文描述： | MROM, RISC MICROCONTROLLER, PQFP208 |
| 封裝： | VQFP-208 |
| 文件頁數： | 26/82頁 |
| 文件大小： | 1101K |
| 代理商： | CL-PS7110-VI-A |
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DATA BOOK v1.5
May 1997
26
FUNCTIONAL DESCRIPTION
CL-PS7110
Low-Power System-on-a-Chip
Figure 1-7. Sample Schematic for Negative V
EE
Control Circuitry
1.2.15 Keyboard Control
A keyboard can be connected using any of the serial channels. The CL-PS7110 provides a seamless
interface for connecting a scanning keyboard. There are column (COL[0-7]) pins for connecting to the 8
columns of the scanning keyboard. The GPIO pins can be used for row addressing; the GPIO pins 0–8
can be configured as a single 8-bit port (PA[0–7]).
1.2.16 GPIO
There are 36 general-purpose pins on CL-PS7110. These pins are user-configurable as input or output.
The 36 pins can be arranged as 4-byte-wide registers (which can also be read back as a single 32-bit
word), and one nibble-wide port (described as Port A, Port B, Port C, Port D and Port E in the device pin
diagram). Four of the I/O pins have extra-high drive output buffers to allow direct drive of an LED, for exam-
ple.
1.2.17 Buzzer Control
There a single pin for buzzer control. When the BZMOD bit of the SYSCON register (described in
Section 3.2.11
) is reset, the bit BZTOG can be used to drive the buzzer directly. Otherwise, Timer 1 can
be programmed to activate the buzzer based on a pre-programmed value.
-V
EE
C2
2.2
μ
10
μ
F
GND
GND
GND
C78
R54
330 k
V
REF
LM339
FB0
DRIVE0
R74
U13D
DRIVE1
FB1
GND
82
81
87
86
100 k
R75
V
DD
100 k
R53
U19
V
DD
L3
47
μ
H
R56
R
100 n
806 k
C44
R64
R65
R63
R62
392 k
200 k
100 k
64
PD4
PD5
PD6
PD7
63
62
61
CL-PS7110
FB1
11
10
13
+
D12
1N5818
100 k
DRIVE1
-
+
TR1
PNP
V
DD
V
DD
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