參數(shù)資料
型號(hào): CL-PS7110-VI-A
廠商: CIRRUS LOGIC INC
元件分類: 微控制器/微處理器
英文描述: Low-Power System-on-a-Chip
中文描述: MROM, RISC MICROCONTROLLER, PQFP208
封裝: VQFP-208
文件頁數(shù): 32/82頁
文件大?。?/td> 1101K
代理商: CL-PS7110-VI-A
DATA BOOK v1.5
May 1997
32
PIN INFORMATION
CL-PS7110
Low-Power System-on-a-Chip
2.2
Pin Description Conventions
Abbreviations used for signal directions in this section are listed below:
2.3
Pin Descriptions
Abbreviations
Description
I
A pin that functions as an input only.
O
A pin that functions as an output only.
I/O
A pin that operates as an input or an output.
Table 2-1.
External Signal Functions
Function
Signal
Name
Signal
Description
Address and
Data Bus
D[0–31]
I/O
32-bit system data bus for DRAM, ROM, and memory-mapped expansion.
A[0–14]
O
Least-significant 15 bits of system
byte
address during ROM and expansion cycles.
A[15]/
DRA[12]–
A[27]/DRA[0]
O
13-bit multiplexed DRAM
word
address during DRAM cycles or address bits 16 to 27
of system
byte
address during ROM and expansion cycles.
Memory and
Expansion
Interface
NRAS[0–3]
O
DRAM RAS outputs to DRAM banks 0–3.
NCAS[0–3]
O
DRAM CAS outputs for bytes 0 to 3 within 32-bit word.
NMOE
O
DRAM, ROM, and expansion output enable.
NMWE
O
DRAM, ROM, and expansion write enable.
NCS[0–3]
O
Expansion channel I/O strobes. Active-low SRAM-like chip selects for expansion.
CS[4–7]
O
Expansion channel I/O strobes. Active-high SRAM-like chip selects for expansion
EXPRDY
I
Expansion channel ready. External expansion drives this low to extend bus cycle.
WRITE
O
Transfer direction: low during reads; high during writes from the CL-PS7110.
WORD
O
Word access enable. Driven high during word-wide cycles; low during byte-wide
cycles.
EXPCLK
O
Expansion clock output. Clock output at the same phase and speed as the CPU
clock. Free-running or active only during expansion I/O cycles.
Interrupts
MEDCHG
I
Media changed input. Active-high door or expansion-change de-glitched input.
NEXTFIQ
I
External active-low fast interrupt request input.
EINT[3]
I
External active-high interrupt request input.
NEINT[1–2]
I
Two general-purpose, active-low interrupt inputs.
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