參數(shù)資料
型號(hào)： CL-PS7110-VI-A
廠商： CIRRUS LOGIC INC
元件分類： 微控制器/微處理器
英文描述： Low-Power System-on-a-Chip
中文描述： MROM, RISC MICROCONTROLLER, PQFP208
封裝： VQFP-208
文件頁(yè)數(shù)： 20/82頁(yè)
文件大?。?/td> 1101K
代理商： CL-PS7110-VI-A
DATA BOOK v1.5
May 1997
20
FUNCTIONAL DESCRIPTION
CL-PS7110
Low-Power System-on-a-Chip
Table 1-3
shows the address mapping for various DRAMs with square and non-square row and address
inputs assuming
two
×
16 devices are connected to each RAS line. This mapping is then repeated every
256 Mbytes for each DRAM bank. nis given by
n
=
0xC
+
bank number
(for example, 0xC for bank 0;
0xF for bank 3, etc.).
2
A4
A12
A25/DRA2
3
A5
A13
A24/DRA3
4
A6
A14
A23/DRA4
5
A7
A15
A22/DRA5
6
A8
A16
A21/DRA6
7
A9
A17
A20/DRA7
8
A19
A18
A19/DRA8
9
A21
A20
A18/DRA9
10
A23
A22
A17/DRA10
11
A25
A24
A16/DRA11
12
A27
A26
A15/DRA12
Table 1-3.
DRAM Address Mapping
Device
Size
Address
Configuration
Total Size
of Bank
Address Range of
Segment(s)
Size of
Segment(s)
4 Mbits
9 Row
×
9 Column
1 Mbyte
n000.0000–n00F.FFFF
1 Mbyte
16 Mbits
10 Row
×
10 Column
4 Mbytes
n000.0000–n03F.FFFF
4 Mbytes
16 Mbits
12 Row
×
8 Column
4 Mbytes
n000.0000– n007.FFFF
n010.0000–n017.FFFF
n040.0000–n047.FFFF
n050.0000–n057.FFFF
n100.0000–n107.FFFF
n110.0000–n117.FFFF
n140.0000–n147.FFFF
n150.0000–n157.FFFF
512 Kbytes
64 Mbits
11 Row
×
11 Column
16 Mbytes
n000.0000–n0FF.FFFF
16 Mbytes
64 Mbits
13 Row
×
9 Column
16 Mbytes
n000.0000–n01F.FFFF
n040.0000–n05F.FFFF
n100.0000–n11F.FFFF
n140.0000–n15F.FFFF
n400.0000–n41F.FFFF
n440.0000–n45F.FFFF
n500.0000–n51F.FFFF
n540.0000–n55F.FFFF
2 Mbytes
256 Mbits
12 Row
×
12 Column
64 Mbytes
n000.0000–n3FF.FFFF
64 Mbytes
1 Gbit
13 Row
×
13 Column
256 Mbytes
n000.0000–nFFF.FFFF
256 Mbytes
Table 1-2.
Physical-to-DRAM Address Mapping
(cont.)
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